The thermometer code (also named as unary code) is useful to extract a vector number and use it to drive several switches. The thermometer code converts a n-bit number into a series of ones followed by zeroes of size 2^n. In this example a 8-bit vector is going to be transformed into 256 signals to drive 256 switches. The binary-to-thermometer decoder is used, instead of the binary-code, to perform smoother transition during most significant bit changing. Continue reading “Binary to Thermometer decoder in VHDL and implemented in Cadence”
Monte Carlo analysis is a statistical way to analyze a circuit. This simulation allows us to test the process variation and mismatching between devices in a single chip or wafer.
As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text.
Real silicon circuits on the dies after the manufacturing process are unfortunately far from behave as an ideal circuit designed on Cadence. This allows do more realistic simulation at the by updating your circuit into a more realistic one based on the physical layout. In this way it is ensured proper functionality of the design and a better representation of the final silicon product behavior.
Here I will resume the most useful keyboard shortcuts or boundkey to use Cadence Virtuoso in an effective and fast manner. Learning bindkeys is the best way to be productive on this complex EDA tool.
This VHDL-AMS block is an ideal comparator, which check if the actual voltage in the input pins above the given threshold is or not. The output is a digital std_logic signal named “result”.
This counter has three digital inputs: enable, reset and a clock signal. Every clock cycle when the enable signal is read as HIGH, the counter will count upwards. When the reset is HIGH at the beginning of every clock cycle, the counter status is reseted to zero (synchronized reset). Continue reading “Counter block in VHDL for CADENCE”
The following current sink vary it current value depending on the 8 bit digital input. For each increment of the input the current increase one step declared as generic parameter in VHDL. For this case the generic parameter is named “rate” and given the value of 0.5 uA. Continue reading “Digitally Controlled Current Sink in VHDL-AMS for CADENCE”