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This VHDL-AMS block is an ideal comparator, which check if the actual voltage in the input pins above the given threshold is or not. The output is a digital std_logic signal named “result”.
The following current sink vary it current value depending on the 8 bit digital input. For each increment of the input the current increase one step declared as generic parameter in VHDL. For this case the generic parameter is named “rate” and given the value of 0.5 uA. [Read more…] about Digitally Controlled Current Sink in VHDL-AMS for CADENCE