How to create a testbench in Vivado to learn Verilog or VHDL

It is very common with the students, which are trying to learn a new programming language, to only read and understand the codes on the books or online. But until you don’t put hands on and start typing your own small programs, compile them, find errors, simulate, etc you will not get the experience to write your own codes and therefore to learn how to program a new language.

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Power-On Reset implementation for FPGA in Verilog and VHDL

The Power-On Reset I an electronic circuit that generates a reset impulse, which sets the entire design to an initial and well-known state after the power supply is detected. It often used with a RC circuit in VLSI in chip-design. In Vivado the Xilinx’s Processor System Reset LogiCORE IP provides this functionality.

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