It is very common with the students, which are trying to learn a new programming language, to only read and understand the codes on the books or online. But until you don’t put hands on and start typing your own small programs, compile them, find errors, simulate, etc you will not get the experience to write your own codes and therefore to learn how to program a new language.
In this article I am going to show how to generate a sinus wave in a FPGA with Verilog and VHDL. I am going to program and demonstrate the functionality with Vivado 2017.4. This is going to be divided into 3 parts:
- Fixed frequency sinus-signal
- Variable frequency sinus signal
The Power-On Reset I an electronic circuit that generates a reset impulse, which sets the entire design to an initial and well-known state after the power supply is detected. It often used with a RC circuit in VLSI in chip-design. In Vivado the Xilinx’s Processor System Reset LogiCORE IP provides this functionality.
Continue reading “Power-On Reset implementation for FPGA in Verilog and VHDL”
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. In these cases FPGAs provide a good solution allowing the implementation of parallel modules, which will process all the information a lot faster than a processor does.
This stepwise tutorial will show how to create a video processing program on the ZYBO board using Vivado HDL.
This counter has three digital inputs: enable, reset and a clock signal. Every clock cycle when the enable signal is read as HIGH, the counter will count upwards. When the reset is HIGH at the beginning of every clock cycle, the counter status is reseted to zero (synchronized reset). Continue reading “Counter block in VHDL for CADENCE”
The aim of this project is to develop the fastest possible PWM generator block using the Zynq FPGA and VHDL programming language. Therefore the constrains are studied to know which are the speed limitations. Several versions are developed with different features and configurable parameters.