Counter block in VHDL for CADENCE

(Last Updated On: March 21, 2018)

This counter has three digital inputs: enable, reset and a clock signal. Every clock cycle when the enable signal is read as HIGH, the counter will count upwards. When the reset is HIGH at the beginning of every clock cycle, the counter status is reseted to zero (synchronized reset).

The schematic for testing:

The simulation in Cadence results:



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