Ideal Comparator in Cadence (VHDL-AMS) for Mixed Signal

(Last Updated On: March 21, 2018)

This VHDL-AMS block is an ideal comparator, which check if the actual voltage in the input pins above the given threshold is or not. The output is a digital std_logic signal named “result”.

A small test bench to prove the functionality was built with two voltage sources as following:

The signals are:

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