As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text.
Plotting data in real time is a very useful task that could be tough, but using the tool KST, I will show how easy it is. The front end look very professional and clean to present your project. KST is a very powerfull and robust solution for plotting live “streaming” data.
Real silicon circuits on the dies after the manufacturing process are unfortunately far from behave as an ideal circuit designed on Cadence. This allows do more realistic simulation at the by updating your circuit into a more realistic one based on the physical layout. In this way it is ensured proper functionality of the design and a better representation of the final silicon product behavior.
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. In these cases FPGAs provide a good solution allowing the implementation of parallel modules, which will process all the information a lot faster than a processor does.
This stepwise tutorial will show how to create a video processing program on the ZYBO board using Vivado HDL.
Here I will explain, how to create a starting project for video processing using the FPGA and VHDL language in Vivado. This is a continuation of the post: “Video Processing with Zybo using the FPGA“, where I explain a bit the basics and background of this project.
Here I will resume the most useful keyboard shortcuts or boundkey to use Cadence Virtuoso in an effective and fast manner. Learning bindkeys is the best way to be productive on this complex EDA tool.
Also called ΔΣ-converter or ΣΔ-converter, this is one of the most used method to get high resolution analog to digital converters (ADC) at a certain speed. This is included in many microcontrollers displacing the typical SAR standard converter. Continue reading “Delta-sigma (ΔΣ) and SAR as standar ADC converter in microcontrollers”
I recently noticed that my diplom thesis is available online on the university repository.
This VHDL-AMS block is an ideal comparator, which check if the actual voltage in the input pins above the given threshold is or not. The output is a digital std_logic signal named “result”.