Power-On Reset implementation for FPGA in Verilog and VHDL

(Last Updated On: March 10, 2018)

The Power-On Reset I an electronic circuit that generates a reset impulse, which sets the entire design to an initial and well-known state after the power supply is detected. It often used with a RC circuit in VLSI in chip-design. In Vivado the Xilinx’s Processor System Reset LogiCORE IP provides this functionality.

If a synchronous reset is executed at system startup, it is possible that there is no clock signal at this time, since the clock source itself may be subject to a reset. Therefore, the synchronous reset can be ineffective.

Often the Power-On Reset (POR) is generated by an external device, for example the watchdog, which monitors the supply voltage or the activity of a microprocessor. Then the POR is also not synchronous to the system clock.

The following circuit generates a reset signal from the external POR (in this example low active) which becomes active high for at least 3 clock cycles and then becomes inactive synchronously with the clock. It is crucial that the reset signal is not deactivated within the setup time of a memory, ie shortly before a clock edge!!!

The external POR signal sets the 3 flip-flops of the shift register asynchronous to ‘0’ (= reset). Since it is asynchronous to the system clock, it is called reset_a and is active low.

After the POR signal has been deactivated, its inactive value ‘1’ is clocked into the shift register as soon as the system clock is present. The first two flip-flops prevent a possible metastable state from affecting the synchronized reset_s signal, otherwise the entire system would be put into an undefined metastable state. After 3 clocks all outputs of the 3 flip flops are set to the value ‘1’, which means that the triple NAND gate changes from the value ‘1’ (active reset_s level) to the value ‘0’ (inactive reset_s level ) changes.

Code implementationsin HDL

With FlipFlops in series:

Verilog

VHDL

The waveform after the simulation looks like:

Using a shift register

Verilog

VHDL

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