Tutorial: How to start a video processing application with Vivado VHDL

(Last Updated On: March 10, 2018)

This stepwise tutorial will show how to create a video processing program on the ZYBO board using Vivado HDL.

C:\Users\Alberto\AppData\Local\Microsoft\Windows\INetCache\Content.Word\DSC00604.jpg

After opening Vivado, first you need to create a new project on your workspace you want to work in.

Click next

Name your project and choose the project location.

Select RTL project

Choose Zybo as a target board or another Zynq board you want to use.

Now create a new block diagram and name it

When the empty block diagram is created, the processing system IP should be instanciated. A new Zynq_Processing_system diagram should be added

Run the block automation to let vivado to connect the dynamic RAM (DDR) and the fixed processor MIO pins.

As in this project the AXI bus is not going to be used, the AXI interface can be removed

On the processing system configuration pannel the clock speed can be adjusted. For this example only one signal clock at 200MHz is needed, as it can be seen on the Dvi2RGB IP datasheet. Therefore the FCLK_CLK0 should be set to 200 MHz.

Now the user application block should be created, or imported. Therefore press ctrl+A or right click on the sources and select “add sources”.

Selecct “add or create design sources”

Create a new file with VHDL with some name, for example VideoProcessing.


Here Vivado ask you to insert the input and output of your block. This can be defined later, but it is good to create at least one input in order to Vivado recognize it as a block and let you instanciate without modifying. The inputs and outputs can be always modified later on the VHDL file.

After that the new module can be instanciated on the block diagram. Right click on the empty diagram and select “add Module…”

Download the IP core from Digilent Github directory [2]. The following files will be needed.

To download visit the repository main page of Digilent and click on donwload to clone it. You will have to be logged in with a gitHub account.

Once downloaded add this IPs to your repository, or create a new folder for your repository.

To add the repository sourcer, we have to go to “project settings” to the “Repository Manager” tab.

Then the new created folder should be added:

Both added IPs should be instanciated to the block diagram:

The RTL module should be added by selecting “add Module” (right click on the block diagram)

Click on the green message “Run connection Automation”

Until now the block diagram should be like this:

The RTL block should be modified with the user define code. Therefore a testing code is inserted:

To insert the code, select the RTL module on the diagram and press F7. The code editor should be now open and there you can insert and edit your code.

Route the diagram as shown.

Add an external pin to the IPs inputs and output. For that right click on the pin and select “make external” Also can be done by selecting the pin and pressing cntrl+T.

Now add two constants for the HDMI configuration

These can be renamed on the property window

Change the value of the constants. For that double click on the module and enter the value. To VDD “Co nst val = 1” and for GND “Const val = 0”

The block diagram is finish and should look like:

The last step is to create a wrapper out of the design_1 Block diagram:
C:\Users\Alberto\AppData\Local\Microsoft\Windows\INetCache\Content.Word\simulation-vivado-zybo-zynq-Wrap.png
C:\Users\Alberto\AppData\Local\Microsoft\Windows\INetCache\Content.Word\simulation-vivado-zybo-zynq-Wrap1.png

The block diagram is ready to synthetize. After that if there were no errors, we can route the pins with the constrain file. For that we go back to “add sources” by pressing the short cut Alt +A.
C:\Users\Alberto\AppData\Local\Microsoft\Windows\INetCache\Content.Word\add-sources-vivavdo-zynq0.png

After the pin definition file is added you can run the implementation. But be aware that the pin name of your pins of your diagram match with the written on the constrain file. If this does not match you can add either the pin name or the constrain file.

Now you are ready to generate the bitstream and load it to the Zybo board.

Constraint file

The pin definition file constrains.xdc

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