An Overview of On-chip Inductors for Integrated Circuits IC. Types, Pro & Cons

Is it possible to integrate Inductors on-chip? What kind of inductors are available in IC? Are they feasible and useful?

Nowadays since the invention of the Integrated Circuit (IC)  in 1959 from Fairchild (now ON Semi), resistors, capacitors, inductors, diodes, transistors or even some kind of sensors can be included on a piece of silicon.

I already talked about the integrated capacitor technologies available on ICs. Now it is turn for integrated inductors 🙂

IC Inductors Challenges

Utilizing inductors at the integrated circuit level present uniques challeges and it is not straighforward.

• Inductors inherently are a very lossy device.
• At lower frequencies, the necessity for large inductors arises, bringing technical unfeasibility challenges within the actual IC technologies.
• Application at low frequencies require large inductors, which are tecnically unfeasible.
• In RF applications, inductors radiate and generate strong electromagnetic disturbances that must be carefully attended.
• Inductors can not be scaled down without compromises their quality factor, limiting their performance in miniaturized IC designs

As you may know, an inductor is just a wire wound around a core (which can be also the air). Integrated Spiral inductors are the most common and straightforward solution. Also, Bondwires inductors can be considered as “integrated” and are going to be discussed here.

Although, inductors can be implanted in the chip, they have two limiting drawbacks:

• low Quality factor
• low Henry value

In this article, the state-of-the-art in integrating inductors on-chip with spiral and bondwires inductors is going to be explained.

Planar Spiral Inductors

Monolithic on-chip inductors are named planar spiral inductors. These on-chip inductors are just metal lines turning around forming spires.

Although they can be built with several metal layers, they are usually built only the top metal layer. To increase the inductance value, they are usually pilled up with simple metal wires routed in spirals.

Planar inductors can achieved low inductance values. But in comparison with on-chip active inductors, they have a better linearity and a low level of noise.

Summarizing

Low quality factor: The ohmic loss is high (specially at high frequencies) due to the resistance of the wires (skin-effect) and the resistance induced by the eddy currents in the substrate. They Quality factor is in standard CMOS is typically below 20.

Low inductance: the inductance is set by the numbers of turns, and this is fixed. So the inductor can not be tunable. The ways to increase the inductance is by adding more turns or stacking several metal layers.

 Large silicon area: Due to the previous reason, adding more number of turns to the inductances  implies a bigger amount of silicon area (that increase a lot the cost of the chip). They are by far the most silicon-consuming components.

 Low self-resonance frequency: The area of the spira is high (due the 2 previous reasons) forming the stray capacitance also high. That means, that the self-resonance frequency is typically in the low GHz range.

 Not available in all technologies: Spiral inductors are not available in low-cost digital-oriented CMOS processes.

Monolithic die with on-chip inductors

Cheap for mass production. No external components are needed.

Bond Wires

A bondwire is the connection cable used to join the pads of the silicon die to the package pins or legs of the package.

By connecting multiple bondwires between bonding pads, an inductor is created. This can be seen easily on the  figure below.

This is made during the chip packaging process and since the bonding step is a must during the chip packaging, these kind of inductors do not add too much extra cost. Although, the packaging process must support internal bondings.

These kind of inductors have low loss due to gold bondwires and higher Q than spiral inductors, but much less than off-chip coils.

The cost of the bondwire inductors is higher than the planar inductors. Each bonding connection costs aprox. 0.18$ at packaging. So each turn would cost 0.32$ [3]

Summarizing

 Not available in all packaging technologies: internal bounding must be support.

Dies must be packaged. On wafer testing during the development is not possible.

Higher Q than spiral inductors

The area below the pads, can be used by other part of the circuit.

Sources:

[1]: “CMOS Active Inductors and Transformers. Principle, Implementation, and Applications”, Fei Yuan. Springer. 2008. Book

[2]: “Modeling, Design, and Characterization of Multiturn Bondwire Inductors With Ferrite Epoxy Glob Cores for Power Supply System-on-Chip or System-in-Package Applications”, Jian Lu, IEEE Transactions on power electronics.

[3] “A 7.1-mW K/Ka -Band Mixer With Configurable Bondwire Resonators in 65-nm CMOS”. Chun-Hsing Li  ; Chun-Lin Ko ; Ming-Ching Kuo ; Da-Chiang Chang. IEEE Transactions on Very Large Scale Integration (VLSI) Systems