A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester. [Read more…] about Solar Cell Verilog Model for Cadence
It is very common with the students, which are trying to learn a new programming language, to only read and understand the codes on the books or online. [Read more…] about How to create a testbench in Vivado to learn Verilog or VHDL
In this article I am going to show how to generate a sinus wave in a FPGA with Verilog and VHDL. I am going to program and demonstrate the functionality with Vivado 2017.4. This is going to be divided into 3 parts:
- Fixed frequency sinus-signal
- Variable frequency sinus signal
The Power-On Reset I an electronic circuit that generates a reset impulse, which sets the entire design to an initial and well-known state after the power supply is detected. It often used with a RC circuit in VLSI in chip-design. In Vivado the Xilinx’s Processor System Reset LogiCORE IP provides this functionality.
[Read more…] about Power-On Reset implementation for FPGA in Verilog and VHDL