This counter has three digital inputs: enable, reset and a clock signal. Every clock cycle when the enable signal is read as HIGH, the counter will count upwards. When the reset is HIGH at the beginning of every clock cycle, the counter status is reseted to zero (synchronized reset). [Read more…] about Counter block in VHDL for CADENCE
The aim of this project is to develop the fastest possible PWM generator block using the Zynq FPGA and VHDL programming language. Therefore the constrains are studied to know which are the speed limitations. Several versions are developed with different features and configurable parameters.