It is very common with the students, which are trying to learn a new programming language, to only read and understand the codes on the books or online. But until you don’t put hands on and start typing your own small programs, compile them, find errors, simulate, etc you will not get the experience to write your own codes and therefore to learn how to program a new language.
In this article I am going to show how to generate a sinus wave in a FPGA with Verilog and VHDL. I am going to program and demonstrate the functionality with Vivado 2017.4. This is going to be divided into 3 parts:
- Fixed frequency sinus-signal
- Variable frequency sinus signal
This stepwise tutorial will show how to create a video processing program on the ZYBO board using Vivado HDL.
Here I will explain, how to create a starting project for video processing using the FPGA and VHDL language in Vivado. This is a continuation of the post: “Video Processing with Zybo using the FPGA“, where I explain a bit the basics and background of this project.
There is many options for Synthesis and implementation in Vivado, which one should I use? Depend on what are you searching for.