Frequently we need to add an external off-chip component to integrate in a simulation in Cadence.
Mixed Signal
Tie Cells in IC Circuits: WHY? schematic and explanations
The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground.
How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-A
Creating a Verilog model cellview in Cadence for a device using a lookup table is a quick and straightforward method to characterize any physical component.
VerilogA Code to Stop a Transient Simulation in Cadence
This auxiliary block in Cadence is a Nice to Have in your Library!
This block stops or finishes a Cadence transient simulation when an output signal reaches a desired value.
Clock Generator in a FPGA: Full code
How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals.
Solar Cell Verilog Model for Cadence
A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester.