How to stop or finish a simulation with a VerilogA command. [Read more…] about VerilogA Code to Stop Simulation in Cadence
Create a Verilog model of a device with a lookup table is a straightforward and fast method if you can characterize the physical device.
A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester. [Read more…] about Solar Cell Verilog Model for Cadence
As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text.
How to write an ideal comparator in Cadence with vhdlams HDL language? The comparator checks if the actual input voltage pin is above the reference voltage or not.
A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations. [Read more…] about Design of a digital Counter in VHDL for CADENCE