Verilog Languaje Post Archives

Solar Cell Verilog Model for Cadence

Cadence, Circuit Design, Mixed Signal, Verilog24 November, 202418 June, 2019 by Alberto L.

A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester.

How to create a testbench in Vivado to learn Verilog

FPGA, Verilog, VHDL24 November, 202431 May, 2018 by Alberto L.

How to start a new Vivado project to create a testbench for programming with Verilog or VHDL languages.

Sinus wave generator with Verilog and Vivado

FPGA, Verilog, VHDL25 May, 202413 March, 2018 by Alberto L.

This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.

Power-On Reset implementation for FPGA in Verilog and VHDL

FPGA, Verilog, VHDL24 November, 202410 March, 2018 by Alberto L.

A power-on reset for an FPGA is implemented in Verilog and VHDL languages.