How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals. [Read more…] about Clock Generator in a FPGA: Full code
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. [Read more…] about The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to create a testbench in Vivado to learn Verilog
How to start a new Vivado project to create a testbench for programming with Verilog or VHDL languages.
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Sinus wave generator with Verilog and Vivado
This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.
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Power-On Reset implementation for FPGA in Verilog and VHDL
A power-on reset for an FPGA is implemented in Verilog and VHDL languages. [Read more…] about Power-On Reset implementation for FPGA in Verilog and VHDL
Basics of Video Processing on the FPGA of a Zybo using VHDL (I)
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. [Read more…] about Basics of Video Processing on the FPGA of a Zybo using VHDL (I)