How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. [Read more…] about The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to start a new Vivado project to create a testbench for programming with Verilog or VHDL languages.
[Read more…] about How to create a testbench in Vivado to learn Verilog
This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.
A power-on reset for an FPGA is implemented in Verilog and VHDL languages. [Read more…] about Power-On Reset implementation for FPGA in Verilog and VHDL
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. [Read more…] about Basics of Video Processing on the FPGA of a Zybo using VHDL (I)
How to set up a video processing project with Vivado and the board Zybo, using the FPGA and programming it with VHDL.