Clock Generator in a FPGA: Full code
How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals. …
FPGA, Mixed Signal, VHDL
VHDL
FPGA, Mixed Signal, VHDL
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. …
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FPGA, Verilog, VHDL
How to create a testbench in Vivado to learn Verilog
How to start a new Vivado project to create a testbench for programming with Verilog or VHDL languages.
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FPGA, Verilog, VHDL
Sinus wave generator with Verilog and Vivado
This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.
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FPGA, Verilog, VHDL
Power-On Reset implementation for FPGA in Verilog and VHDL
A power-on reset for an FPGA is implemented in Verilog and VHDL languages. …
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Electronics, FPGA, VHDL
Basics of Video Processing on the FPGA of a Zybo using VHDL (I)
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. …
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Electronics, FPGA, VHDL
Video Processing with Vivado VHDL and ZYBO Board (II)
How to set up a video processing project with Vivado and the board Zybo, using the FPGA and programming it with VHDL.
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Cadence, Circuit Design, Mixed Signal, VHDL
Design of a digital Counter in VHDL for CADENCE
A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations. …
Cadence, Circuit Design, Mixed Signal, VHDL
A variable digital controlled Current Source in CADENCE
A digital model and an analogue circuit of a dependent or adjustable current Source is created in Cadence.
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