Also called ΔΣ-converter or ΣΔ-converter, this is one of the most used method to get high resolution analog to digital converters (ADC) at a certain speed. Nowadays is often included in the microcontrollers displacing the typical SAR standard converter.
The working principle of the ΔΣ-adc is the charge balancing, by using incremental steps. This converter is in reality based on a 1-bit converter, which iterates.
- Highest linearity
- Inherit monotonous
- Medium speed
The Delta-sigma modulator is the heart of the device and converts the analog voltage into a pulse frequency (in the picture labelled as”rate k”).
The ADC converts the mean of an analog voltage into the mean of an analog pulse frequency. Later the pulses are counted in a fixed interval so that the pulse count divided by the predetermined interval gives an accurate digital representation of the mean analog voltage. This interval can be chosen to give any desired resolution or accuracy.
Why ΔΣ is so accurate?
The ΔΣ-converter uses oversampling and noise shaping techniques to obtain a highly accurate resolution.
Oversampling in ΔΣ-converter
We can see the Dependency between SNR (signal to noise ratio), oversampling and ADC order , versus the relative frequency on the following graph. To design a converter a trade of between oversampling rate and a higher order have to take into account. When the oversampling is high, you need more frequency at sampling, with more expensive and accurate clock jitter and more power consumption at the end. On the other hand when a high order is used, large areas on the silicon device are required.
The output of the Delta-Sigma converter is a bit stream of one bit. To convert this to a value, on a manner to read or use it, there are different possibilities:
- Frequency counter:
The instantaneous output frequency of the delta – sigma modulator is proportional to the input voltage. By measuring this frequency during a given period, we get the mean value of the input voltage during that period.
- FIR- filter or high performance 16 bit audio converter:
input of the adder. We get an n – bit output in this manner.
- IIR-Filter or low-cost audio codecs:
This converters, for example the AD73322, use the so called sinc-cubed filter.
SAR – (Succesive Approximation Register)
The SAR architecture enables high-performance low power ADCs, although there are variations in the SAR architecture that vary slightly for different designs and search algorithms. The basic schema of a SAR converter is:
- good ratio speed/power
- Uses a small silicon area –> inexpensive and possibility to parallelise or pipeline it.
- A bad decision of the algorithm at the beginning or middle of the loop is critical and bring to the result a big error. The algorithm can not recover from this error.
How is work?
Another more convenient form of SAR to reduce the power consumption is the binary weighted capacitor implementation. This is possible because the capacitors are really small and therefore the current over them also.
Once the conversion is finished by the Delta-Sigma or SAR converter, the data from the register should be transmitted to the CPU…
How are the external ADC connected to the microcontroller?
Lecture notes of Analog Circuits Design
How a Delta-Sigma works-part1