The delta-sigma ADC and the successive approximation register are the standard integrated analog to digital converter in microcontrollers.
This post is an overview of these 2 types of converters with the advantages, drawbacks, functionality, etc
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Delta Sigma ADC converter
The delta sigma converter (ΔΣ-converter or ΣΔ-converter) is one of the most used methods for high-resolution analog to digital converters (ADC) at a certain speed. Nowadays it is often included in the microcontrollers displacing the typical SAR standard converter.
The working principle of the ΔΣ-adc is the charge balancing, by using incremental steps. This converter is in reality based on a 1-bit converter, which iterates.
Disadvantages:
How does delta sigma ADC works?
The delta-sigma modulator is the heart of the device and converts the analog voltage into a pulse frequency (in the picture labelled as”rate k”).
The ADC converts the mean of an analog voltage into the mean of an analog pulse frequency.
Later the pulses are counted in a fixed interval so that the pulse count divided by the predetermined interval gives an accurate digital representation of the mean analog voltage. This interval can be chosen to give any desired resolution or accuracy.
Why is the delta sigma ADC so accurate?
The ΔΣ-converter uses oversampling and noise shaping techniques to obtain a highly accurate resolution.
The oversampling in a ΔΣ-converter
The trick or benefit of oversampling is that the total noise power equal, but it is distributed to a larger frequency band while using a higher sampling frequency. Therefore, the quatization noise is smaller (orange band) because is distributed into a larger spectrum. If the oversampled signal is filtered to the non-oversampled bandwidth, the SNR increases.
Noise shaping: The quantization noise is moved to the outside of the signal frequency range by increasing the order of the converter, so that the SNR increased.
We can see the Dependency between SNR (signal to noise ratio), oversampling and ADC order , versus the relative frequency on the following graph. To design a converter a trade of between oversampling rate and a higher order have to take into account.
When the oversampling is high, you need more frequency at sampling, with more expensive and accurate clock jitter and more power consumption at the end. On the other hand when a high order is used, large areas on the silicon device are required.
The output of a delta sigma ADC
The output of the Delta-Sigma converter is a bit-stream of one bit. To convert this to a value, on a manner to read or use it, there are different possibilities:
- Frequency counter:
The instantaneous output frequency of the delta – sigma modulator is proportional to the input voltage. By measuring this frequency during a given period, we get the mean value of the input voltage during that period.
- FIR- filter or high performance 16-bit audio converter:
They use a linear phase FIR filters, for example the AD1836. The 1 bit value of the modulator is multiplied by an n-bit coefficient, which is the
input of the adder. We get an n – bit output in this manner.
- IIR-Filter or low-cost audio codecs:
This converters, for example the AD73322, use the so called sinc-cubed filter.
SAR ADC – (Succesive Approximation Register)
The SAR architecture enables high-performance low power ADCs, although there are variations in the SAR architecture that vary slightly for different designs and search algorithms. The basic schema of a SAR converter is:
Disadvantages:
How is work?
The analog input voltage (Vin) is held on a track/hold block to keep the analog value for a certain amount of time. A binary search algorithm is performed, the N-bit register is first set to a midscale at the initial state (1000 0000 when using 8-bits converter). This forces the DAC output (Vdac) to be half of the reference voltage (Vref/2).
Then a comparison is made to determine if analog input is greater than Vdac. If Vin is greater than Vdac, the comparator outputs a logic “1” and the most significant bit of the register remains at 1. On the other case, if Vin is less than Vdac, the comparator outputs a logic “0” and the most significant bit of the register is reseted to zero.
The SAR control logic then moves down to the next bit and repeat the binary search algorithm with another comparison. The sequence continues until the the less significant bit is tested, the conversion is completed and the result of the conversion is available in the register.
I tried to summarize this algorithm on a flow diagram, maybe is more clear:
Another more convenient form of SAR to reduce the power consumption is the binary-weighted capacitor implementation. This is possible because the capacitors are really small and therefore the current over them also.
Once the conversion is finished by the Delta-Sigma or SAR converter, the data from the register should be transmitted to the CPU…
Extra: How are the ADC connected to the microcontroller?
Nowadays most of the external ADCa are connected with an SPI bus.
This is because it is faster than the bus I2C. I2C has a maximum clock speed of 400 KHz and need 4 bytes to transmit a 16 bits ADC lecture.
On the other hand, using the SPI protocol, 3 or 4 byte are needed to transmit 16 bit, but the maximum speed can reach up to 35 MHz using the high speed.
To get higher speeds, the communication protocol LVDS (Low Voltage Differential Signal) is supported by many SAR-ADCs. This is employed a lot in the FPGAs with clocks rate up to 200MHz.
Sources:
- Lecture notes of Analog Circuits Design
- How a Delta-Sigma works-part1
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