The following current sink vary it current value depending on the 8 bit digital input. For each increment of the input the current increase one step declared as generic parameter in VHDL. For this case the generic parameter is named “rate” and given the value of 0.5 uA.
The digital controlled current sink is a current sink, which drains a proportional current in function of the digital input signal. For this case an 8-bit vector is used as an input. The minimum step-size of the current source is 1uA. For example; a CurrentInput of 30 will generate a current sink of 30 uA.
For each increment of the input the current increase one step declared as generic parameter in VHDL. For this case the generic parameter is named “rate” and given the value of 1 uA.
entity Csink is
rate : real := 1.0e-6
signal CurrentInput : std_logic_vector(7 downto 0);
terminal sink,drain : electrical
architecture vhdlams of Csink is
quantity IR through sink to drain; --IR is the current between both ports
signal converted : integer; --For convert the input std_vector
converted <= CONV_INTEGER((CurrentInput)); --Convert the std_logic_vector to integer
IR == real(converted)*rate;
For test this module the control signal (std_logic_vector) is provided from the counter block.
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After the simulation:
An analogue model was created for the mixed signal circuit, to compare it with the digital model.
The thermometer or unary code is needed in the current sink to drive the 256 branches of 1 uA. The thermometer code converts a n-bit number into a series of ones followed by zeroes of size 2^n. In this case we are transforming an 8bit input vector into a 256 output vector.
The thermometer coder block is written in VHDL and tested on the next Figure.
entity thermo is
vector_in : in std_logic_vector(7 downto 0);
vector_out : out std_logic_vector(255 downto 0)
architecture vhdlams of thermo is
signal salida : std_logic_vector(255 downto 0) := (others => '0');
variable intermediate: integer range 0 to 255;
intermediate := CONV_INTEGER((vector_in));
salida <= (others => '0');
for i in 0 to intermediate loop
salida(i) <= '1';
vector_out <= salida;
A separated test bench was used for the current sink, as shown in the Figure 15. The previous explained counter is here reused as stimuli to create an increasing and decreasing ramp as shown in the Figure 16.
The test signal is a ramp like the following:
Functionality test of the thermometer coder
Digital versus analogue model
Theoretically, the digital and analogue model should behave identically. But this should be tested. For the current sink, the analogue model performs similar, but slightly different.
The digital model behaves as programmed, each step of the input is translated into current linearly, as shown in the following Figure.
In the following Figures, the digital and analogue model are compared: