Often we need to model physical devices to simulate them in Cadence or other EDAs. Here I explain with an example how to write a Verilog code for a model using a table.
The easiest way to create a model, is to obtain or calculate the equations that control the behave of the device. Knowing the mathematical model, it is easy to implement it as a model in Verilog-ams.
What happen if I don’t know the equations, I am not able to calculate them or they are quite complex?
The solution is to implement a lockup table with the measured results. Verilog will automatically interpolate between the given points.
This is made using the function $table_model. Of course, we need to have (accurate) measurements of the behavior with different inputs.
The table with all the data can be stored on an external file or as a matrix.
The easiest and comfortable way is to save the model data in a file, so you can update or exchange it in the future. Also it is much straightforward to write or edit a file than enter the data via a hard-coded matrix.
How do I write the file?
The file should be in “*.tbl” format. For example: my_data.tbl
2 easy golden rules:
- # is used for comments.
- The columns should separated by tabs or spaces like the following file:
In the previous example, the input data has only one input, let’s say x, and an output f(x). We could also have multiple inputs: x, y and f(x,y).
Note that to have a 2-D matrix, for each x point you need at least 2 values of y. If not the compiler could not interpolate (or extrapolate) and it gives you an error.
In this other picture you can see a 3-D matrix:
The data file should be stored in the same path of the cell (inside the library) in the folder \veriloga
Note (as it is mentioned in the Verilog Language Reference page 84), the data file is not refreshed after a change. If you want to modify the data file, you may modify the name of the file to force an update.
For this example I added an enable signal (with active high).
Full Verilog Code
Here is the full verilogams code of this example:
// Engineer: Alberto Lopez
// Description: Verilog model of the solar cell photodiode
// Change history: 11/Sept/2019
module SolarCell_Table( EN, Vsolar, GND);
parameter real light =1;
parameter real vthreshold = 0.6;
real iout, itemp;
real i1,i2, i3, i4, i5;
en = 0;
@(cross(V(EN) -vthreshold,1)) begin
if(V(EN)>=vthreshold) en = 1;
else en = 0;
Vcp = V(Vsolar,GND)*1000;
i1 = -$table_model (Vcp, "ph4_1.tbl", "1C")/1000000;
i2 = -$table_model (Vcp, "ph4_2.tbl", "1C")/1000000;
i3 = -$table_model (Vcp, "ph4_3.tbl", "1C")/1000000;
i4 = -$table_model (Vcp, "ph4_4.tbl", "1C")/1000000;
i5 = -$table_model (Vcp, "ph4_5.tbl", "1C")/1000000;
// if(itemp <0 ) iout = itemp;
// else iout = 0;
1: iout = i1;
2: iout = i2;
3: iout = i3;
4: iout = i4;
5: iout = i5;
default: iout = 0;
if(en== 0) iout = 0;
I(Vsolar,GND) <+ iout;
Simulating the system with an enable signal:
Step by step:
- Create a new veriloga cell view, then write the code.
- Create the data file and move it to the library path.
- Then compile the code, and when it compiles without any error, Cadence will ask you to create a symbol with the pins.
Then you have your fully functionally veriloga model.