Design of a IC Thyristor-based ring oscillator in Cadence

IC thyristor-based oscillators offers an ultra-low-power consumption alternative for applications where accuracy isn’t important.

In this tutorial, we are going to design and test with Cadence Virtuoso a thyristor-based ring oscillator from scratch, presenting the schematic diagrams and simulation plots.

Let’s start from the beginning

What is a Thyristor?

A thyristor is a device with 3 terminals Drain, Source and Gate.

The functionality is similar to transistors, but with the difference that when it is triggered with a high voltage at the gate, it remains ON. The thyristor must stay ON forever theoretically, but… due leak currents, after some time is elapsed, it flips and turns off. This property is exploited in this case in our benefit.

We can consider the thyristor as a one-way transistor

Ring of Thyristors

A thyristor ring oscillator works identically to an inverter-based ring oscillator.

A cascaded odd number of inverters connected in a closed-loop

For this ring, we will use 3 elements, the minimum.

The delay of each thyristor-based inverter depends on the leakage current of the CMOS transistor, which discharges the node slowly until the threshold voltage is met and it turns. Therefore the delayed time is much much slower than a regular CMOS inverter.

Consequently, ring oscillators generate a clock in the MHz range, while thyristor-based oscillators work in the Hz range.

Another advantage is the very very low power consumption. It only takes a minimal amount of current during the transition to load the nodes. The static consumption is zero.

The main drawback is the fact that the delay is proportional to the leak current, which is unknown and it is usually not properly modelled. Also, it has a strong dependency on process parameters and temperature variations

As a curiosity, ring oscillators were first presented in 1995 in the Solid-State Circuit Journal. [1]

Schematic diagram

The schematic of this slow clock is presented on the pic below:

Start-up

A small circuit with a capacitor and 2 transistors is used to force the oscillation at the beginning. One of the problems of the ring oscillators is to ensure the first cycle of oscillation and avoiding the metastability. Later on, it oscillates itself and forever.

In real life, a fabricated silicon integrated circuit with a ring is so infrequent that it remains in a metastable position. Due to impurities and the fact that all the transistors are not 100% identical, the oscillator will be naturally provoked.

In simulation, the transistors are identical, with the same exact ideal behaviour. This causes the metastabilities on simulations. But, in IC design we don’t want uncertainties or at least the minimum of them.

CMOS Thyristor

Several CMOS structures can be used for thyristors. The chosen structure of this example is a CMOS thyristor with footer transistors because of the power consumption [2].

Output Stage

This is just the typical inverter chain at the output to reduce the rise time, and to give the capability to drive more power to the output. This stage must be designed for each application.

Simulations

The test bench is quite simple and it can be seen in the following picture:

After a transient analysis, it can be seen in the wave diagram with the oscillations.

The average current consumption of the clock is only 1.9nA for a frequency of 43 Hz. The FoMof the oscillator (I/freq) is 0.044nA/Hz.

The startup circuit functionality can be seen on the following wave diagram:

The Output signal and the inner signals are displayed on the next simulation diagram:

Frequency adjustment

This is only an example, the frequency must be modified to each application.

Both capacitor sizes determine the capacitance of the node and therefore, how much energy must be discharged through the leak. Hence, it varies inversely with the frequency.

More capacity — > slower clock — > less frequency

With a parameter simulation we can see it easier. The multiplier parameter is varied for the values 1, 2, 5, 10, 20 and 50.

The results can be different:

Thus, the leak current is proportional to the frequency.

More leak current — > more frequency

Layout

The layout is extremely important in circuits like this that rely on such small capacitances. The stray capacitors of the paths and vias would modify the behaviour of the design.

Therefore it is important to run post-layout simulations before its fabrication. Also, corners and Monte Carlo simulations are important in these fragile circuits.

Sources

[1]: Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang and Wonchan Kim, “A low-voltage, low-power CMOS delay element,” in IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 966-971, July 1996, doi: 10.1109/4.508210.

[2]: (extract) Thyristor-based oscillator. Extract of my Thesis with a Monte Carlo analysis of the thyristor type election.

[3]: A. K. Mahato, “Ultra low frequency CMOS ring oscillator design” 2014 Recent Advances in Engineering and Computational Sciences (RAECS), 2014, pp. 1-5, doi: 10.1109/RAECS.2014.6799627.