Integrate circuits technology allows creating many types of devices on the silicon die. The most common devices are transistors, diodes, resistors or capacitors.
In microelectronics, where the area means money, the capacitors are the bulkiest device. In a certain technology, the most important parameter for capacitors is the capacitance density. The density is measured in fF/µm² and varies from 0.2 to ~7, depending on the technology.
How are the ideal Capacitors?
IC-Capacitors in silicon are far from being ideal… but how is an ideal cap?
The properties of an ideal capacitor:
- high quality factor (Q) / low losses
- high breakdown voltages
- capacitance being voltage-independent
- high area capacitance
- low parasitic capacitance
- low leakage currents
Taking into account the capacitance formula:
to obtain high-density capacitors in integrated circuits, three factors could be changed:
- A better isolator with higher dielectric constant
- Shorter distances between layers
- Increase the area
The distance between layers depend on the technology, but they are not constant and the thick can not be determined with precission. That is why the capacitors have typically around ~20% of error from the nominal value and bring the large nominal capacitance variations.
The die-area is a very valuable factor in chip-design, and should be reduced as much as the design allows it. Remember area = money.
MIM Capacitor (Metal-Insulator-Metal)
It is formed by two parallel metal layers and has a high k-dielectric between them. The button layer forms a small parasitic cap with the substrate.
This type is the most used, because of the high capacitance per unit area with the lowest parasitics. The drawback is that they require more process steps during the fabrication. Mainly, a new mask and step are added to deposit the insulator between the metal layers. Therefore, a fabrication process with MIM caps is more expensive than others using only MOM-caps.
They can be single, double, triple, etc. It depends on the number of layers of metal and insulators. The thickness of the insulator layer is in the range of 25 nm (depending on the fabrication technology).
The quality factor is very high because both plates are made out of metal and the voltage dependency is negligible.
For example, in X-Fab XT018 technology cmm3t or cmmh4t with a density between 1 and 6 fF/µm². In TSMC18, mimcap_2p0_sin with C = 1.00 fF/µm².
They are very similar to the MIMs caps but with an oxide layer between metals is usually made by interdigiating metal layers with the process oxide. So the capacitance is created in two places: laterally capacitance with the other fingers and vertically capacitance with the other layers.
They have a lower capacitance per unit area, but they are cheaper than MIM.
Transistors can be used as a cap using the thin oxide layer from the gate as an insulator. The Gate acts as the top plate and the Drain and Source as the button plate.
They are also known historically as MOS-Capacitors (Metal-Oxide-Semiconductor)
The drawback is that if the voltage at the gate varies, the depletion area changes at the gate varying the dielectric properties and modifying the capacitance. So, the MOS capacitor’s value is very dependent on the applied DC voltage.
The capacitance per unit area is higher than the MIM caps, because the insulator of the gate (SiO2) is much thinner than the insulator between the metal layers. But the variation with the voltage is a big disadvantage.
They are useful for local supply decoupling where the DC voltage is constant. Another drawback is the parasitic resistance of the bottom plate.
Metal Fringe Capacitors
They use only one metal layer, relying on the side capacitance property and the matching is better than the MIMs caps.
For example, in X-FAB technology csf3 or csft4.
This kind of caps are still an object of study and development. Deep narrow pores are made in the silicon substrate to gain more surface and create high-density capacitor saving die area.
These are useful to save area, but they are not available in many technologies (almost any). The capacitance density is up to 700 nF/mm² by a submicrometer pores array. The pores could be up to few hundreds nanometers big.
Diodes (pn-junctions), when they are reverse-biased, introduce a small capacitance, which varies a lot with the voltage applied.
MOS-caps and pn-caps are very voltage-dependent capacitances.
The density of the junction capacitances is around 1pF/um2.