How to stop or finish a simulation with a VerilogA command.
This VerilogA block/code for Stop the current simulation in Cadence Virtuoso depending on analog conditions.
This block is perfect when you need to perform multiple long simulations, for example, corners or Monte Carlo. You will save a lot of simulation time
VerilogA Code
This block will stop the simulation when an analog signal arrives at a determinate value.
/////////////////////////////////////////////////////////////////////////// // Engineer: Alberto Lopez // // Description: stop the simulation when the input voltage arrives to a minimum value // // Change history: feb/2021 // ///////////////////////////////////////////////////////////////////////////// `include "constants.vams" `include "disciplines.vams" module FINISH_run( vin, GND ); inout GND; input vin; electrical GND; electrical vin; //Parameters parameter real tiempo = 1u; //refreshing time for the Verilog code parameter real MIN_VOLTAGE = 2; //Min voltage level to trigger the integer flag; analog begin @(initial_step) begin flag = 0; end @(timer(0,tiempo)) begin if( V(vin,GND) > MIN_VOLTAGE ) begin flag = 1; //only for testing purposes $finish(0); //command to stop the current simulation end end end //analog endmodule
How does it work
I created a simple testbench with the previous VerilogA block and a voltage source with a ramp signal.
First, I will comment out the VerilogA code to see the “input” signal raw.
Note: to comment out or ignore a block in Cadence, you must press the keybinds CTRL+del. Other Cadende Keybind can be found on this list.
The input signal with 4ms simulation time looks like:
Activating the Verilog code and re-running the simulation. We can see that, although the simulation time was 4ms, the block stops the simulation at 360us.
Reading the log window, we can notice that the simulation has been externally stoped.
Stop with a predefined delay
In this variant, the code will stop the simulation after some time when the condition is fulfilled.
Code:
/////////////////////////////////////////////////////////////////////////// // Engineer: Alberto Lopez // // Description: stop the simulation when the input voltage arrives to a minimum value // // Change history: feb/2021 // ///////////////////////////////////////////////////////////////////////////// `include "constants.vams" `include "disciplines.vams" module FINISH_run_delay( vin, GND ); inout GND; input vin; electrical GND; electrical vin; //Parameters parameter real tiempo = 1u; //refreshing time for the Verilog code parameter real MIN_VOLTAGE = 2; //Min voltage level to trigger the FINISH parameter real DELAY_TIME = 1000; // number of "tiempo" steps to execute the stop action integer flag; integer cnt; analog begin @(initial_step) begin flag = 0; cnt = 0; end @(timer(0,tiempo)) begin if( V(vin,GND) > MIN_VOLTAGE ) begin flag = 1; //only for testing purposes end if (flag == 1) begin cnt = cnt +1; if (cnt == DELAY_TIME) begin $finish(0); //command to stop the current simulation end end end end //analog endmodule
Pavankumar
How to generate sine look up table in verilog code
Alberto L.
Hello,
Your can check my other post, where I talk about sinus wave generation with look-ups tables
Best Regards
ART
I tried to use $finish(0) in an MC sim, but that ends the simulation after the first run (nom run). it doesn’t end the current run only. is there any other command to do so?
Pedro
I’ve got a similar problem. When using VerilogA module with $finish in MC, every run ends up with “sim error”.
Pedro
In the simulator log I found this:
(…) To stop the current transient analysis without stopping the simulation, use the ‘$finish_current_analysis’ function instead of ‘$stop’.
I’ve replaced $finish with $finish_current_analysis and now it works also for MC 🙂
Alberto L.
Thanks for the valuable info 🙂
wellgood
Hi ALberto,
I am trying to implent a “delay” function in verilogA model, e.g. an oscillator, because the oscillator should not run before others power up. Could you please give me some advice?Thanks!
Alberto L.
Hello Wellgod,
I would implement a trigger with the POR signal you may have instead a delay-based model.
Best Regards
Alberto