Real silicon circuits on the dies after the manufacturing process are unfortunately far from behave as an ideal circuit designed on Cadence. This allows do more realistic simulation at the by updating your circuit into a more realistic one based on the physical layout. In this way it is ensured proper functionality of the design and a better representation of the final silicon product behavior.
Think that (almost) everything you draw involve the creation of parasitics, simplifying resistors and capacitors. Every single route on the metal or via layer is in fact a resistor, a small resistor on the best cases, but at the end of the day a resistor. On the same way every two conductors or conducting surfaces split by a insulator implies the creation of a stray capacitor.
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Depending on the circuit, this can have a huge influence on the final behavior of the design. Parasitics may cause among others:
- Impulse Response drop
- More capacitive loading
- inductive coupling
- increased delays
Following the backend design flow:
Layout generation >> DRC >> LVS >> Parasitic extraction >> Post Layout Simulation >> Final Layout.
The backannotation is performed after the parasitic extraction. Your should get a file named “<filename>_extracted” in Cadence. After that, ideally, it would be nice to make a full chip back-annotation, but this is not any more supported by current tools due the high required computer power. To solve this, digital back-annotated parasitics are transformed into delays by the “Timing Calculator”. These digital delays are standardized on “Standard Delay Format” (SDF) -file. On the analog blocks parasitic capacitances and resistances are added to the schematic.