Several methods can be used to measure with Cadence Virtuoso the offset voltage of an operational amplifier (op-amp) using only simulations. …
Why Offset errors? How to Simulate the DC Offset in Op Amps with CadenceRead More »
The Cgd (gate-drain parasitic capacitance) in a CMOS common-source amplifier plays a significant role, especially at high frequencies. …
Cgd Gate-Drain Parasitic Capacitor effect on a CMOS Common Source AmplifierRead More »
Simulating and carrying out a proper noise analysis in Cadence is important to prevent undesired post-tapeout issues. …
How to make a Noise Analysis in Cadence step-by-stepRead More »
Charge Injection is caused by the switching action of the MOSFET, resulting in a brief injection of charge into the signal path, leading to voltage glitches. …
What is Charge Injection and Cancellation Techniques in Analog CMOS Switches (T-Gates)Read More »
Learn how to calculate the gain of a basic 2-stage CMOS Op-Amp using Cadence Virtuoso. Explore theoretical analysis, transient simulation, and AC simulation methods to accurately measure op-amp performance, stability, and frequency response in analog circuit designs.
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How to Calculate the Gain of an Operational Amplifier with CadenceRead More »
Struggling to find key parameters for transistors in Cadence? Learn how to quickly and effectively characterize NMOS devices with this comprehensive guide. …
How to Characterize NMOS Devices in Cadence: A Step-by-Step GuideRead More »
What are the differences between NMOS and PMOS devices in a CMOS technology? …
Physical Comparison between NMOS vs PMOS TransistorsRead More »
The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground. …
Tie Cells in IC Circuits: WHY? schematic and explanationsRead More »
Why are the LDOs mainly built with pmos as a pass transistor and not with nmos devices? …
Nmos and Pmos LDO: Differences and Advantages on each TopologyRead More »
To generate complementary clock signals from a single clock signal, the so-called “non-overlapping” block is needed.
Often, 2 complementary clock signals are needed, where only one clock edge is active at a time. Meaning that the rising and falling edges of the clock are separated in time. …
Where can we obtain the ON-voltage or forward-bias voltage in bipolar transistors, which is around 0.7V? …
Where is the 0.7V voltage drop of BJTs coming from?Read More »
There are many types of comparators, in this example a comparator with hysteresis is analyzed and simulated. …
Design a CMOS Comparator with Hysteresis in CadenceRead More »
