FPGA Archives - Mis Circuitos

Clock Generator in a FPGA: Full code

FPGA, Mixed Signal, VHDL24 November, 202423 June, 2020 by Alberto L.

How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals.

The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)

FPGA, Mixed Signal, VHDL24 November, 202427 March, 2019 by Alberto L.

How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado.

How to create a testbench in Vivado to learn Verilog

FPGA, Verilog, VHDL24 November, 202431 May, 2018 by Alberto L.

How to start a new Vivado project to create a testbench for programming with Verilog or VHDL languages.

Sinus wave generator with Verilog and Vivado

FPGA, Verilog, VHDL25 May, 202413 March, 2018 by Alberto L.

This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.

Power-On Reset implementation for FPGA in Verilog and VHDL

FPGA, Verilog, VHDL24 November, 202410 March, 2018 by Alberto L.

A power-on reset for an FPGA is implemented in Verilog and VHDL languages.

Basics of Video Processing on the FPGA of a Zybo using VHDL (I)

Electronics, FPGA, VHDL24 November, 20247 January, 2018 by Alberto L.

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Processing video frames require a large amount of computation power, therefore processors may not be powerful enough.