How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. [Read more…] about The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
A power-on reset for an FPGA is implemented in Verilog and VHDL languages. [Read more…] about Power-On Reset implementation for FPGA in Verilog and VHDL
Processing video frames require a large amount of computation power, therefore processors may not be powerful enough. [Read more…] about Basics of Video Processing on the FPGA of a Zybo using VHDL (I)
There are many options for Synthesis and implementation in Vivado, which one should I use?