Why Offset errors? How to Simulate the DC Offset in Op Amps with Cadence

Several methods can be used to measure the offset voltage of an operational amplifier (op-amp) using only simulations in Cadence Virtuoso.

The offset voltage in op-amps is an inherent characteristic of the circuit, resulting from mismatches in transistor characteristics, overdrive voltages, and layout imperfections.

What is “Offset” in Op. Amps?

The “DC-offset” error is unavoidable. Simply put, it is impossible for an operational amplifier to be perfectly balanced, which generates a DC offset error.

They are usually modelled as an ideal op-amp plus a DC voltage source on one input, as depicted in the following symbol.

Why does the Offset exist?

Offset voltage arises due to inherent mismatches and imperfections in the internal components of the op-amp, particularly within the transistors that make up the input differential pair.

• Threshold Voltage (Vth​) Mismatch: The two input transistors should ideally be identical. However, due to process variations during fabrication, their threshold voltages of the transistors may differ slightly. This difference causes the transistors to require slightly different gate-source voltages (Vgs) to conduct the same current, leading to a small voltage difference at the input terminals that produces a voltage offset.
• Transistor Geometry Variations: Any mismatch in the W and L dimensions between the transistors in the differential pair leads to unequal current distribution, resulting in an offset voltage.
• Process Gradients: Across the silicon wafer, there can be slight variations in doping concentration, oxide thickness, and other parameters. These process gradients contribute to the offset.
• Parasitic Effects: Differences in parasitic capacitances and resistances in the layout, caused by variations in routing, lead to mismatches and offset errors.
• Mismatches Due to Temperature: If the two transistors in the differential pair experience different local temperatures or have different temperature coefficients, their characteristics will diverge as the temperature changes, leading to an offset voltage.
• 1/f (Flicker) Noise: This low-frequency noise can contribute to the offset voltage, especially in low-frequency applications.

How to Reduce Offset in Diff. Pairs

Here the most effective ways to minimize the offset errors:

• Use Larger geometries. Larger devices smooth out the effect of the edges imperfection on the transistors fingers. However, keep in mind that ,the bigger the devices are, the slower the transistors will switch due to higher gate capacitance.
• Common centroid: A well-executed layout with a common centroid, compensates for the inevitable process gradients across both axes of the silicon wafer. However, it is still not 100% effective but it mitigates the effect.

Moreover, techniques like trimming, auto-zeroing, and chopping can reduce or compensate for the offset voltage down to the 1 uV level. They are typically employed in precision applications to further reduce the impact of offset voltage.

How to Measure the Op- Amp offset error

The most straightforward and simplest methods to measure the offset of an Op. Amp with a simulation are studied in this article with a practical example.

The Op. Amp. Circuit

For this example, I chose a standard 2-stage operational amplifier including some enabling switches. The op-amp. is partially asymmetric, which infers an offset-prone design (valid for this case).

Offset Calculation Methods

1- Manually setting the offset

The op- amp is connected in open-loop configuration. The inputs are tied to a common bias level, which is typically half of the supply voltage (Vsupply/2). This ensures that the inputs are balanced and any output deviation is due to the inherent offset of the op-amp.

At one input, the minus one in this example, is connected to a DC source, which is swept until the output voltage is centered to the vsupply/2.

The DC vdc source used in this example to compensate the offset is V20. The increments must be small to accurately calculate the offset.

The test bench is depicted in the schematic below. The voltage source V20 has a parametrized dc voltage with the parameter “voffset”.

The common mode voltage, in this case, labeled as vref, which is chosen vsupply/2 (1.8V/2=900mV).

The value of “voffset” is parametrized with a starting estimated range, in this case from -2mV to 2mV. The range is later iterated depending on the simulation results.

For the simulation, we can use a DC simulation or a long enough transient simulation (to avoid the influence of the own op.amp. delay).

DC simulations are preferred versus transient simulations, because they are much faster and precise, but in dc simulations, we have to make sure that the op-amp. is biased properly.

In the plot of the results of the DC simulation, we plot the Vout voltage vs the “offset” parameter to check where the output is equal to vdd/2. In the example below, the offset voltage is estimated to be 585uV.

For double check and confirm the results, I like to perform a transient simulation will confirm the obtained value.

I set the previous obtained offset value to the dc vdc source, 585uV, and perform a long transient simulation. The output voltage must be balanced to vsupply/2.

2- Output Calculation with the Gain

This method to measure the offset in an op- amp. is only valid when we know the value of the dc gain. I explained it in other article How to Measure the Gain of an op-amp with simulations.

The setup is done connecting both inputs are to Vsupply/2 or another bias level. The output voltage is measured.

The offset at the output is the deviation, the difference between the output voltage (Vo) and the bias voltage (Vsupply/2).

The input-referred offset voltage can be calculated dividing the previous deviation by the DC gain:

The input-referred offset voltage (Vos)​ represents the small voltage difference between the inputs of the op-amp that is causing the output to deviate from its ideal balanced value.

3- Unity-Gain Buffer Connection

Configuring the op-amp. under test in unity gain buffer mode, as depicted below. The output is feedback to the inverting input (minus), and the positive input (+) connected to the input voltage.

In this configuration, any voltage difference between the inputs, which is the offset voltage, will be seen directly at the output.

In a perfect op-amp with no offset, the output would exactly match the input voltage.

This method will give you the possibility to include the offset value as an output metric, which will be very useful to make corners, MC, etc.

The test bench can be seen on the following schematic:

To add an output “offset” equals to the output voltage minus the reference voltage.

The results of simulating the previous test bench, with a simply PVT corners are:

In this article, we have explored various methods to measure the offset voltage of an op-amp using Cadence simulations.

As the Offset Voltage is an inherent characteristic of op-amps and unavoidable…

…understanding this offset is crucial for designing robust analog circuits!!