Miller compensation is the most popular technique to ensure frequency stability. By adding a feedback capacitor between amplifier stages, it shifts the dominant pole to a lower frequency, improving Phase Margin and system stability.
However, Miller compensation comes with trade-offs such as reduced Bandwidth, delays the output voltage response and other potential negative effects on power supply rejection ratio (PSRR).
In this article, we explore the insights of Miller compensation, its advantages and disadvantages, and design guidelines.
A circuit is “frequency compensated” after the modification of the open-loop transfer function to make the closed-loop amplifier stable at any desired value of the closed-loop gain.
The simple Miller compensation method is the most popular and straightforward, but not the only, for example nested Miller, NGCC, etc
An inherent problem with Miller capacitor is that it delays the output voltage and thus the negative feedback to the input stage
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Frequency Behavior of a Circuit
The frequency behavior can be determined by the circuit’s poles and zeros.
The pole derived from a node is determined by the effective resistance and capacitance from the node to ground.
To shift a certain pole to higher frequencies, there are two options: increase the resistance or the capacitance of the node.
- Increasing the resistance is difficult without affecting the performance of the amplifier. Moreover, the noise is significantly increased, which raises the overall noise figure of the system.
- Increasing the capacitance attached to the node is much easier, and the way to go. However, we must keep in mind that integrated caps tend to occupy large silicon areas. The Miller multiplication effect helps to solve this issue.
Why is Frequency compensation Needed?
When designing a circuit, we need to guarantee stability, so that the op amp will always operate in a stable manner and will not oscillate when negative feedback of various amounts is applied.
We need to ensure a phase margin to avoid instabilities with any kind of input signal, spurious signals or perturbations, especially at higher frequencies.
Single-stage amplifiers are typically designed to have a single dominant pole, so they behave as a single-pole system for the operation bandwidth. However, two or three-stage amplifiers require frequency compensation due to the presence of two or more high-impedance nodes.
Pole Splitting Method
The simplest method is called “pole splitting”, “Direct Miller Compensation” or “Dominant Pole Approach”. The behavior of the system is converted into a single-pole.
Pole splitting: The lower pole is moved inwards while the higher pole is pushed out. Pushing out the second pole to the right is very beneficial, resulting in a higher phase margin and compensated open-loop gain.
It consists of shifting the first dominant pole to a lower frequency to make it cross the 0dB line (unity gain) with the second dominant pole. Therefore, phase margin is 45º at the critical point, and the system behaves as a single-pole circuit.
In two-stage amplifiers, a feedback capacitor (Cc) is added across the two stages. This causes the pole formed at the internal node to be shifted to a lower frequency and thus become dominant, while the pole formed at the output of the amplifier stage is moved to a very high frequency and thus becomes less dominant.
Here is where the Miller effect comes into play. An equivalent larger capacitor can be attached to the internal node using a much smaller real capacitance thanks to the multiplicative Miller effect.
where Av is the gain of the second stage and C_F is the feedback capacitor between both gain stages.
Although, there are other more complex techniques to provide stability to the system, they aim to solve some drawbacks of the Simple Miller compensation. For example, Indirect Miller, Nested Miller, NGCC, etc
Advantages and Disadvantages of Miller Compensation
✔ The Miller capacitor is much smaller than the equivalent compensation capacitor referred to GND.
Undesirable consequences:
Adding the capacitance shunting a transconductance, add an additional zero.
Reduces the Bandwidth.
Reduces the PSRR (Power Supply Rejection Ratio) because when a cap is connected between the gate and source, a diode-connected transistor is formed at high frequencies.
Circuit Implementation: Design Guidelines
Implementing the new feedback capacitor between the stages.
Summarizing, the resulting poles after applying the pole splitting technique obtained by inspection are:
The transconductance of the second stage (Gm2) plays a very important and effective role in controlling the phase margin and compensating the circuit.
From the previous equations of the compensated circuit poles, wp1 and wp2 depend directly and inversely on Gm2. As mentioned before, the dominant pole, wp1, must be shifted to lower frequencies and the non-dominant pole, wp2, must be pushed out to higher frequencies.
The Feedback Capacitor Cc
The value of Cc must be chosen between C1 (the parasitic capacitances of node 1) and the output capacitance (C2 + Cload, but normally Cload >> C2).
Initial Guess of Cc
A good starting point for Cc is 30% to 50% of the output load (C2+Cload).
1pF can be generally an initial value for standard cases.
Note that a too large Cc capacitance will slow down the speed of the circuit and will not provide necessary additional pole splitting, but a smaller GBW.
The effect of the Cc capacitor on the pole splitting can be seen on the following plot. The second pole saturates at a certain point and will have negligible effect of the wp2 pole.
The gain bandwidth product (GBW) = Av ·wp1
To achieve stability and a good Phase Margin, Gm2 must be greater than gm1. To increase the Gm2/Gm1 ratio (see the plot of the wp2/wu1 ratio vs Phase Margin). This implies that the current in the second stage will be much larger than the first stage and that most of the current does not contribute to the GBW.
Given the previous equations:
Drawbacks: Feedforward Zero
The compensation capacitance (Cc) connects the outputs of the first and second gain stages, and leads to a right-half plane (RHP) zero.
A new zero is created because a capacitor shunts a transconductance.
By definition, the zeros are formed at any value of “s” which makes the output equal to zero. Isolating the second stage, as depicted in the following plot, the equivalent small-signal circuit is:
To get zero output voltage, the output current flowing through Rout must also be zero. Therefore, the current flowing through the capacitor Cf is equal to Gm·Vin (with opposite signs).
Therefore, the zero due to the Miller capacitor is:
The “Nulling Resistor”
When a capacitor is added between the second and first stages, a new zero is introduced in the circuit. That means, we introduce a new path for the current at certain frequencies.
Let’s remember that the impedance of capacitors decreases with the frequency, easing the current flow through this path. The impedance of a capacitor follows the formula Z=1/jωC
So, the behavior of a capacitor changes with frequency. At low frequencies, a capacitor acts as a blocking element (high impedance), while at high frequencies, it allows current to pass through (low impedance).
How to solve this problem?
Adding a resistance R in series with C reduces or solves the problem of the phase lag caused by the new zero. The resistor limits the current with a minimum impedance at high frequencies, when the capacitors impedance is low.
Apart from the Miller compensation technique, there are other, more complex techniques known as indirect compensation. For example, adding a voltage buffer in series with the compensation capacitor in the feedback path or including a common-gate stage to block the feedforward component of the compensation current while achieving pole splitting.
The resistance is often referred to as “Nulling resistor” or “Lead compensation”.
The small-signal circuit:
Considering that Vout2 = 0 (zero condition) and applying KCL equations at the output node, with the iout = 0, the zero is now placed at:
With the resistance Rz, the transmission zero can be moved to a less-harmful location (below the 0dB line). The resistor can control the zero location, by moving it from the Right Half-Plane (RHP) zero to infinity or to a Left Hand Plane zero (LHP).
Zero at infinity. If we want to allocate the zero at high frequencies, or ideally at infinite frequencies, the resistor must be set to Rz = 1/Gm2.
The best design practice in amplifiers is to push the zero to be at infinity. By eliminating the zero, it improves the frequency response and settling time.
Even if the resistance is not perfectly equal to 1/gm2 (to push the zero to infinite), a perfect cancellation is not required, since if the resistance difference is small, it will push the zero to very high frequencies obtaining similar results.
Zero at LHP. The zero can be moved to the LHP If the resistance is greater than 1/Gm2, the zero is placed at a negative real-axis location and the phase it introduces improves the phase margin. However, the zero can indirectly produce noise amplification and slow down the settling time.
In addition, the zero can be used to cancel the wp2 and improve the Phase Margin. Although, a real zero-pole cancellation is difficult to achieve in a practical fabricated circuit.
Moreover, a first-order system (overdamped) is slower than the second-order system
In other circuits, such as voltage regulators, the zero can be used intentionally to improve the Phase Margin, but at the cost of a lower Bandwidth and longer settling time.
The extra zero adds around 15-25 deg. of extra phase margin without compromising the gain-bandwidth.
MOS implementation of the Resistor
The nulling resistor, implemented as a real poly resistance, will suffer from different process variations compared to the second-stage output transistor.
The workaround is to implement the resistor as a MOSFET transistor biased in the triode region. Therefore, the Rz tracks the 1/gm of the second stage transistor, so the zero will be placed independently of the process and temperature variations.
The transistor type must be the same as the output stage (nmos or pmos) and the value of resistance must be 1/gm2.
It is better to place the MOSFET on the left side of the Miller capacitance, so that the output node has more swing. Therefore, source and drain have smaller variations and Vgs is more constant.
Conclussions
The Miller compensation technique in amplifier or op-amps design is basic to achieve certai stability and improving phase margin. Although, there are always trade-offs, including reduced Bandwidth and PSRR degradation. However, a careful design and optimization ensures amplifier stability and performance while balancing speed and bandwidth.
Biography
[1] Indirect Compensation Technique for Low-Voltage CMOS Op-amps. Vishal Saxena (ECE Dept., University of Texas at Austin) and R. Jacob Baker (ECE Dept., Boise State University)
[2] Design of Analog CMOS Integrated Circuits. Behzad Razavi
[3] CMOS Analog Circuit Design. Phil Allen and Doug Holberg.
