Monte Carlo analysis is a statistical way to analyze a circuit in VLSI.

This simulation allows us **to test the process variation and mismatching** between devices in a single chip or wafer.

*Let’s talk a bit more about Monte Carlo…*

Contents

## Difference between Corners analysis and Monte Carlo

The **Corner analysis** simulates your design with the minimum and maximum value of each parameter. But it does not reproduce the mismatching between devices!

We can say, that corner analysis makes the problem much harder than it really is. It simulates **extreme cases, that in real fabrication process will never occur**, because of the c**orrelation between parameters** are **not** taken into account.

A standard corner analysis can involve around 65 simulations, taking the maximum and minimum of the process variables:

**CMOS thickness:**wp, ws, wo, wz.**Resistor value:**wp, ws.**Capacitor value:**wp, ws.**Temperatures:**(typ.)-20 to 85ºC**Voltage supply:**depend on your supply source, etc.

Typical number of simulations: tm+ 4CMOS*2RES*2CAP*2TEMP*2Vsupply = 65

**Where:*

- ws
*= worst speed* *wp = worst power*- wo
*= worst one (Fast NMOS & Slow PMOS)* - wz
*= worst zero (Slow NMOS & Fast PMOS)*

For example, if the CMOS gate oxide thickness is big for NMOS, it will be also big for the NMOS. It is not realistic to simulate the case when the thickness of the NMOS is minimum and the PMOS is maximum.

**Corner analysis guarantees that the circuit will work**, of course, under all possible consideration, **but it overdesigns your circuit**.

## Monte Carlo Simulation in Circuit Design

**Monte Carlo** analysis is** based on statistical** distributions. It realistically simulates mismatching and process variation. On **each** **simulation** **run**, it **calculates every parameter randomly** according to a statistical distribution model. With this analysis, you will see in which region your circuit will work most of the time.

The **drawback** of Monte Carlo is the large **number of simulations** required to have acceptable results. It should be **at least 250 **to have a significant sample, but the minimum amount of simulations is not trivial (it follows the statistical model), but as a thumb rule, the more simulation the more significant the test is.

The **amount of simulations to run with Monte Carlo**, is **much higher** comparison than the Corner analysis.

Coming back to the previous example with the gate oxide thickness:

In the corner analysis it is simulated the worst case of the **minimum and maximum** values of the thickness parameter resulting in a variation of the threshold voltage:

But in real fabrication cases, if the NMOS is thin, the PMOS transistor will have also similar thickness. This area is shown in the yellow region.

Another type of corner analysis is known as **“statistical corner models”**, here thousands of real produced wafers are measured. Now the statistical corner analysis **considers correlations of map parameters**. This analysis **improves the Monte Carlo** pure statistical method with the feedback of the real wafer measurements.

** Example of Monte Carlo simulation in Cadence**

In **this example, a clock is going to be simulated**. This clock has a configurable frequency output from 0.84MHz to 1.88MHz depending on a digital input of 4 bits (16 steps).

First, we **make sure that the simulation is working** fine in **nominal conditions** and try to shorten the simulation time as much as possible. If you want to run hundreds or even thousands of simulations, you have to optimize your computational resources.

- Reducing the amount of time (in the ~microseconds range normally) to be simulated for each run.
- Adjusting carefully the resolution steps.
- Selecting only the minimal amount of nets to be saved. But they have to be the minimum necessary to interpret the results and detect where the problem may come from.

In the following picture, the **nominal results for the clock** are shown. The frequency f_0 and f_15 are the values to be tested on the simulation. The nominal values are 836kHz and1.89MHz. Let’s see later how much do they change with the process variations…

Before Monte Carlo, normally a corner simulation is performed, in order to have a preview of the worst case and see the bounded of the Monte Carlo simulation. For this example, the Process Corners simulations looked like:

To proceed with the Monte Carlo:

First, select “Monte Carlo Sampling” (as the picture below shows) and choose the number of simulations on the configuration window:

Later go to the **Corners set-up**, as shown in the picture below, and choose the parameters you want to vary, Usually, the temperature and other parameters. In my cas**e, I want variations on the temperature** (-20-to+85°C) and in VDD (the power supply from 1.1V to 1.3V). Then **depending on the technology** you use, the model files will vary. In this example I used 350µm from AMS.

In this** other config example**, I used **TSMC 180µm**. I used MC column for Monte Carlo simulation and TT for regular corners simulation. Also, more corners set-up are nice to have, for example to vary only some parameters for special cases you may have. In the next example I have the column MIM to vary only the mim-capacitors

**Deactivate the nominal simulation** because we already run and saved it. Then, run the Monte Carlo pressing the green play button.

The results “Yield” window will appears similar to the picture below. In this window, the average, standard deviation, and other statistical parameters are shown.

In Monte Carlo, a histogram plot is used to see graphically the results. For this, click on the histogram icon and then select “histogram” as shown in the screenshot below.

A new window will prompt, and there **you can play with the parameters** or selecting **which data you want to plot**. If you want to combine all the cases you plotted (in my case 4 cases because of 2 temperatures and 2 VDD). You can press “Combine” to plot all together as shown in the next picture:

Then you can export the graph** choosing a white background. **This is very useful and will give you way better appearance when you insert it in your documentation or reports:

**Another Example of Monte Carlo with ADE-XL**

In this other example, a cascade circuit is going to be used to make the Monte Carlo simulation.

First, add the Dc- simulation to save the operation point of the circuit.

To have a good performance, you can put many jobs in parallel, depending on how many cores does your machine has. For this example, I was using an 8 core machine, so I set 8 simulations in parallel.

Go to Options>> Job setup.

Make a DC-simulation a plot the currents.

Add these values from the calculator into the output window in the ADE XL.

Copy this expression and paste them on the ADE XL.

You can add them by Outputs>>Setup

You should get something like. Delete every corner and leave one, that we are going to use as a reference.

We want to make the Monte Carlo Simulation for the nmos transistor, we chose the model cmosmc (Monte Carlo). If we wanted the Monte Carlo for the resistor you should choose “resmc”.

Select it on the Data View.

Go to options for the Monte Carlo Simulation

Set the configuration parameters. Set to process if you want to check the changes on the process in the electrical parameters. If you want to test the changes by matching on the transistors, select then Mismatch. And the number of points, start with something low, for testing, then you can increase it to a larger amount of simulations.

After the simulation, you can right-click and select “histogram” to plot the results.

For a larger number of simulations:

monglebest

Can you provide more detail regarding the models? I am mainly interested in how to setup a monte-carlo simulation from scratch.

Alberto L.

Hello Monglebest, I dont understand which models do you need. Here I explain how to set up the Monte Carlo from scratch

Regards. Alberto

Alberto L.

I am quite bus right now, but when I have more detailed information i will update the post!

Best Regards

terry kenny

Hi Alberto,

Very thorough walkthrough based on Cadence Virtuoso. The one thing that seems to be missing in every article I look at is how to determine the number of monte carlo samples required when setting up the simulation. Showing which information you used (ie; # tail points, confidence interval, sigma desired, etc.) and how you used it would make this article very useful.

Alberto L.

Hello Terry,

Yes, you are right, this is a big topic. For this article I intended to focus on how to implement the Monte Carlo Analysis with Cadence. To know the minimum amount of points necessary, it is more statistical-related topic, that could be covered in other post.

Thanks for the feedback.

Alberto

Sennan

Hello,

First I would like to thank you for your nice block, it is very useful to me

I have some questions please,

You have assumed that corner analyses is overdesigning our circuit, that is why MC simulation is a better method to evaluate the design, however, I saw you including the corners (WP, WS, WZ, WO)again in your MC setup, why you included it ?

I also saw you mixing corners in corner simulation like putting WS of a resistor model with WO of mos or capacitor, is that realistic?

Thank you

Alberto L.

Hello Sennan,

In Monte Carlo, you chose “Monte Carlo Sampling” and also later in the corners column, I’ve chosen

cmosmcfor CMOS, which is meaning Monte Carlo for the cmos variations, what I wanted in this case.You can read the word Corners, but they are not really that. Also, you can combine them in order to reduce the number of statistical simulations.

Hope that it helps you.

Best Regards, Alberto

Senan

Dear Albert,

Thank you for your fast response and help,

I now got it, you have deactivated the corners column in the time of MC simulation.

The second part of my question is still not clear,

I understand the meaning of WS, WO, WP and WZ for the MOSFET, but I don’t know what does it mean for resistors and capacitors?

Secondly, I see you are making combination of the possible corners, like ressitor with WP corner will be simulated with MOS with WS corner or any other different corners , is such of combination is possible ?

Thank you once again

Best Regards

Alberto L.

Hello,

Yes, for this case ws, wo, wp and wz makes no sense for resistors and caps only for active CMOS. That is why i set them to “tm”.

Yes, you can combine them

Jody Podwoski

It was helpful. Keep on posting!

Uma Kulkarni

Hi Alberto,

this is a great page indeed. I find your post on Monte Carlo analysis very crisp and clear. Thanks for that!

Will you please explain what do you mean by “worst one”and “worst zero”?

Alberto L.

Hello Uma,

Worst One means that the NMOS is fast and the PMOS is slow. Also, idem for Worst Zero: Slow NMOS & Fast PMOS

Just in case the WP and WS are meaning:

WP: worst power (fast)

WS: Worst Speed (Slow)

Best Regards

Alberto