How to set up a video processing project with Vivado and the board Zybo, using the FPGA and programming it with VHDL.
VHDL
Design of a digital Counter in VHDL for CADENCE
A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations.
A variable digital controlled Current Source in CADENCE
A digital model and an analogue circuit of a dependent or adjustable current Source is created in Cadence.