The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground.
Nmos and Pmos LDO: Differences and Advantages on each Topology
Why are the LDOs mainly built with pmos as a pass transistor and not with nmos devices?
What are the Operation Region of Transistors in Cadence [1, 2, 3 or 4]
How to know the region of operation of a single transistor in Cadence? What are the meaning of 0, 1, 2, 3 and 4 Regions in terms of cutt-off, saturation, sub-threshold, etc
2-phase Non Overlapping Block for Oscillators
Generating complementary clock signals from a single oscillator signal is straightforward with the so-called non-overlapping block.
Let’s analyze it!!
Where is the 0.7V voltage drop of BJTs coming from?
Where can we obtain mathematically the ON-voltage or forward-bias voltage in bipolar transistors, which is around 0.7V?
How to convert a Cadence Schematic Image into White diagram
Often we deal or receive a black background the typical black-background Cadence schematic that we wish to convert to a white-background Schematic… How?