A typical problem in integrated circuits is distributing a digital signal to a very large node, such as clocking for registers, memories and counters. The propagation delays and skew must be minimized to avoid malfunctions.
Cascaded of 2 RC Low-Pass Filters in Series
When two first-order RC filters are cascaded, the overall transfer function is not simply the product of two individual RC filter transfer functions… WHY?
Why Offset errors? How to Simulate the DC Offset in Op Amps with Cadence
Several methods can be used to measure the offset voltage of an operational amplifier (op-amp) using only simulations in Cadence Virtuoso.
Cgd Gate-Drain Parasitic Capacitor effect on a CMOS Common Source Amplifier
The Cgd (gate-drain parasitic capacitance) in a CMOS common-source amplifier plays a significant role, especially at high frequencies.
How to make a Noise Analysis in Cadence step-by-step
Simulating and carrying out a proper noise analysis in Cadence is important to prevent undesired post-tapeout issues.
What is Charge Injection and Cancellation Techniques in Analog CMOS Switches (T-Gates)
Charge Injection is caused by the switching action of the MOSFET, resulting in a brief injection of charge into the signal path, leading to voltage glitches.