A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester. [Read more…] about Solar Cell Verilog Model for Cadence
Design of a cmos Comparator with Hysteresis in Cadence
There are many types of comparators, in this example a comparator with hysteresis is analyzed and simulated. [Read more…] about Design of a cmos Comparator with Hysteresis in Cadence
How to change the wire colour in Cadence
Change the color of some wires in Cadence Virtuoso can be useful in schematics with a lot of wires. [Read more…] about How to change the wire colour in Cadence
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. [Read more…] about The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
Active Filters: 2nd order Tschebychev Bandpass
A second order active bandpass filter by cascading two staggered tuned first order bandpass filters is shown, built and tested. [Read more…] about Active Filters: 2nd order Tschebychev Bandpass
How to sniff a BLE communication and decode it: Reverse Engineering
Intercept Bluetooth communication of smart gadgets (for example fitness devices) is a nice idea to have cheap BT sensor nodes. I will explain how to sniff and decode your Bluetooth Low Energy Data from your sensors. [Read more…] about How to sniff a BLE communication and decode it: Reverse Engineering