Mixed Signal Design Archives - Page 2 of 2

The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)

FPGA, Mixed Signal, VHDL24 November, 202427 March, 2019 by Alberto L.

How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado.

How to Setup the gedit text editor as default in Cadence for Code Highligh

Cadence, Circuit Design, Mixed Signal24 November, 202426 January, 2018 by Alberto L.

As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text.

Ideal Comparator in Cadence (VHDL-AMS) for Mixed Signal

Cadence, Circuit Design, Mixed Signal24 November, 202430 November, 2017 by Alberto L.

How to write an ideal comparator in Cadence with vhdlams HDL language? The comparator checks if the actual input voltage pin is above the reference voltage or not.

Design of a digital Counter in VHDL for CADENCE

Cadence, Circuit Design, Mixed Signal, VHDL24 November, 202429 November, 2017 by Alberto L.

A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations.

A variable digital controlled Current Source in CADENCE

Cadence, Circuit Design, Mixed Signal, VHDL24 November, 202428 November, 2017 by Alberto L.

A digital model and an analogue circuit of a dependent or adjustable current Source is created in Cadence.