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Basics of Video Processing on the FPGA of a Zybo using VHDL (I)

Electronics, FPGA, VHDL24 November, 20247 January, 2018 by Alberto L.
c users alberto appdata local microsoft windows i

Processing video frames require a large amount of computation power, therefore processors may not be powerful enough.

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Video Processing with Vivado VHDL and ZYBO Board (II)

Electronics, FPGA, VHDL24 November, 20246 January, 2018 by Alberto L.
c users alberto appdata local microsoft windows i

How to set up a video processing project with Vivado and the board Zybo, using the FPGA and programming it with VHDL.

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Ideal Comparator in Cadence (VHDL-AMS) for Mixed Signal

Cadence, Circuit Design, Mixed Signal24 November, 202430 November, 2017 by Alberto L.
word image 7

How to write an ideal comparator in Cadence with vhdlams HDL language?  The comparator checks if the actual input voltage pin is above the reference voltage or not.

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Design of a digital Counter in VHDL for CADENCE

Cadence, Circuit Design, Mixed Signal, VHDL24 November, 202429 November, 2017 by Alberto L.
counter symbol

A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations.

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A variable digital controlled Current Source in CADENCE

Cadence, Circuit Design, Mixed Signal, VHDL24 November, 202428 November, 2017 by Alberto L.
Current sink digitaly controlled symbol

A digital model and an analogue circuit of a dependent or adjustable current Source is created in Cadence.

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