Design of a cmos Comparator with Hysteresis in Cadence

There are many types of comparators, in this example a comparator with hysteresis is analyzed and simulated.

What is the function of hysteresis in a comparator?

By using the threshold we can reduce the glitches on the output caused by the small ripple of the input signal. When the compared voltages are similar then the output is going to flicker if we do not implement a minimum hysteresis. And, of course, multiple transitions in control signals have to be avoided.

The hysteresis is essential to compare noisy signals or similar voltages.

The schematic

The proposed circuit is based on a two-stages open-loop comparator, but adding an internal positive feedback to accomplish the hysteresis. [1] It is a differential-to-single-ended comparator with one stage output buffer (if needed, more output buffers can be added).

The basic topology can be seen in the schema:

The following 2 schematics are implemented in Cadence. Both are the same, they have just a different representation. Maybe the second representation is more clear and understandable.

In this topology, two kinds of feedback can be found with the inputs (IN- and IN+): positive and negative. The negative feedback is through the transistors M1 and M2. The positive feedback is on the transistors M14 and M15.

The ratio between M1 and M15 will determine the overall feedback sign. To have hysteresis, the ratio mult_M15/mult_M1 should be greater than 1.

In a normal comparator, we need to consider two cases: when the currents in M0 and M3 are different but neither is zero, and when one of the input transistors has a current equal to the sink (IPOL in the following case) and the other current is zero.

Comparator Test Bench

For test the behaviour of this comparator, a capacitive load of ~1pF is attached to the output. The bigger the output cap is set, slower the response is going to be. To improve the driving capabilities of the comparator, you may only add an incremental chain of buffers at the before the output of the comparator. For my case with one small inverter was enough for the performance required.

• The bias current is set to 80nA.
• The technology used in this case is TSMC 180nm general purpose.

In this testbench, I attached several voltage sources to the positive input. By this way, I can comment out (ignore) the source I don’t want to use. So I can configure and modify the input source easily.

To see several hysteresis, I will sweep different transistor ratio between the positive and negative feedback. For that, I set a variable named “mult”, which I control how much current flow into the positive feedback.

After the simulation

We can see, that the bigger the ratio between M15 and M1 is, greater is the hysteresis.

To graphically represent the hysteresis, normally the sweeping input voltage is plotted versus the output. This shows better the called bistable characteristic.

That can be done in Cadence!! by clicking on the menu: Axis>> Yvs Y.

For the case of mult = 20, the trip voltage is approx. 1.02V and 1.98V, which can be seen better in the following graph:

Current behaviour

The current wave diagram helps a lot to understand what is happening on the comparator, here a screenshot:

One side hysteresis

For that the size of the transistor M14 was reduced to mult = 1 and the M15 was sized to mult = 20. As the following schema:

The results show how when in+ is less than I- (attached to 1.5V), we obtain more hysteresis because of the feedback of In+ is weaker

To obtain more hysteresis, you may play with the multipliers of M14 and M15, as well you may increase the length of M1 and M2 (or even M0 and M3)

[1] CMOS Analog Circuit Design. Douglas R. Holberg, Phillip E. Allen