Noise is one of those things that every analog designer fights against sooner or later. It limits how small signals can be, reduces the SNR, and becomes especially painful in low-voltage and high-precision circuits.
Noise sets a minimum signal level for a given performance parameter.
In this article, I’ll go through the main noise sources in MOSFETs — thermal and Flicker noise — and explain how they affect analog circuits.
We’ll also look at practical concepts:
- gate-referred noise
- cascoded transistors
- source followers
- kT/C noise
- dominant noise contributors
- trade-offs between noise, bandwidth, power consumption.
In another previous post, I wrote about the different kinds of noise affecting IC circuits. Also, we did some simple noise analysis in Cadence.
Today, in this article, we are going to discuss how the MOSFET noise can be modeled, estimated and mitigated.
MOSFET Noise Model & Equations
MOSFET transistors have 2 dominant sources of noise: Thermal and Flicker noise.
The sources of noise of a MOSFET transistor can be modeled and simplified with the sum of the thermal and Flicker noise.
Let’s see each source one by one.
Thermal Noise
The thermal noise is caused by thermally excited random motion of carriers.
It can be modeled as a current source parallel to the channel or as a voltage source at the gate.
where γ (gamma) is ⅔ for long-channel MOSFETs and nearly 1 for short-channel devices.
Note that the relation between In and Vn is gm (not gm^2!!)
We see that the power spectral density of the thermal noise is uniform across frequency meaning that it contains the same noise power per hertz at all frequencies. This behaviour is commonly referred to as white noise.
Flicker Noise
The Flicker, also called 1/f noise, is caused by material defects. Particularly by traps near the Si/SiO2 interface that randomly capture and release carriers.
The input-referred gate noise of a MOSFET transistor can be modeled as:
where Kf is the flicker noise coefficient.
You can also derive the output-referred noise by multiplying by the transistor transconductance (gm):
The Flicker coefficient (Kf) is a highly technology-dependent parameter. For example in a 0.8um tech node, the values of Kf for pmos and nmos are very different [1]. Therefore, often pmos devices are preferred over nmos.
Wrapping up thermal and Flicker noise together and referring to the gate, we obtain:
where the first term is the Flicker noise and the second one is the thermal noise.
Noise in MOSFETs in a Circuit
Depending on the function of the MOSFET, the noise can be more dominant or even negligible.
Input or Gate-referred Noise
The input-referred noise is a fictitious quantity (it does not physically exist in the circuit) that is used to represent the equivalent contribution of a noise source at the input of a transistor.
Gate-referred noise is therefore commonly used to model the equivalent contribution of a specific noise source at the transistor gate. However, this approximation is only valid when the gate current is approximately zero, i.e., at low and medium frequencies.
Noise in Cascoded Transistors
The noise in cascoded transistors can be neglected. They have a very small contribution that can be ignored without introducing significant error.
Considering a gate-referred voltage source for both flicker noise and thermal noise, the gain from the gate to the output is very small compared with the overall circuit gain. This gain is a degenerated common source with a large degenerated resistance (ro).
Due to this low voltage gain, often, the noise contribution of cascoded devices is often ignored in the total equivalent noise calculations. In the following folded-cascode op-amp, the transistors M6-9 can be neglected for noise considerations.
Dominant Noise Sources
The input signal experiences the same gain as any noise source applied at the gate of the input transistor. Therefore, noise generated by the input devices follows the same signal path and is amplified equally, making these devices especially important in noise analysis.
In general, we can consider dominant noise sources those located in high-gain signal paths.
Source Follower Noise
The Source Follower or Common Drain stage introduces noise directly into the signal path without the benefit of signal gain. We can say that SF simply adds noise to the noise floor.
The SF stage injects its own noise directly into the output signal path.
In critical low-noise signal paths, it is preferred to avoid source followers
In comparison, the Common Source stage amplifies the signal and it introduces additional noise, same as SF. But the overall SNR of the Common Source can be better preserved or even improved due to the gain.
Trade-offs
In general, noise directly trades off with power dissipation and bandwidth.
Bandwidth
The total integrated noise is obtained by integrating over bandwidth. Therefore, increasing bandwidth allows more noise to pass. Also we can say that reducing the bandwidth decreases the total integrated noise.
That is why low-noise systems often use narrow-band filtering.
Power
To reduce noise circuits usually need more biasing currents.
The thermal noise of a transistor is modeled as:
Since gm is proportional to the drain current, more current means larger gm and therefore less noise.
Higher current → larger gm → lower input-referred noise
Supply Voltage VDD
The supply voltage does not affect to generate more noise, but it affects the signal amplitude and therefore the SNR.
Reducing the supply voltage reduces the achievable SNR.
New short channel technologies with reduced supply voltages degrade noise performance. In the following equation, we can see how the SNR is affected by Vdd.
The challenge is that modern short-channel CMOS has worse SNR for similar noise levels.
Noise in Resistors and Capacitors (The interesting KT/C phenomenom)
Before, we mentioned that the thermal noise is generated only by resistive elements. But the fact is that in real circuits, every node is associated with a capacitance to ground. This capacitance limits the bandwidth over which the resistor noise is integrated. [2]
For a simple RC circuit, the resistor generates white noise, but the capacitor acts as a low-pass filter. When the total integrated noise is calculated over frequency, the result becomes [Section 7.2.1 Razavi]:
where k is Boltzmann constant and T is the temperature.
Resistance generates thermal noise, but capacitance determines the total integrated noise at a node.
The result is that the kT/C noise can only be reduced by increasing the node capacitances, but this has important limitations in analog circuits.
But increasing the capacitance has a cost in higher charging and discharging current, meaning increasing the power consumption for a given bandwidth.
For example, for a 1pF capacitor, the total rms noise associated to that node is 64uV.
Conclusions & Takeaways
Reduce the number of noise contributors
The noise produced by Cascoded transistors are negligible in their contribution to the output noise for most applications, especially at low and mid frequency.
Avoid SF in the signal path. They provide no voltage gain.
As a general rule of thumb, avoid devices without gain in the signal path. They induce a bad noise performance. The gain of the devices in the signal path must be high.
gm. Maximize the gm in the signal path and minimize on the current sources.
Amplifiers devices: (maximize gm)
- maximize Id
- small overdrive
- wider W
Current sources devices: (minimize gm)
- large overdrive
Noise is often proportional to kT/C
In differential circuits, the noise of the half-equivalent circuit is also the half of the full symmetric circuit.
For multiple uncorrelated noise sources in a circuit, the total noise can be obtained by superposition.
In general, more power means less noise.
I hope you found this article interesting and useful.
If you want to continue learning about noise in analog ICs, you can also check my previous related articles about the different types of noise in integrated circuits and some basic noise analysis examples in Cadence.
Sources
[1]: TAMU-ELEN-474 2008 Jose Silva-Martinez and Sam Palermo. Texas A&M University.
[2]: Razavi. Section 7.2.1. Design of Analog CMOS Integrated Circuits.
