How to Create a Spice model of a discrete component in Cadence
Frequently we need to add an external off-chip component to integrate in a simulation in Cadence. …
How to Create a Spice model of a discrete component in CadenceRead More »
Frequently we need to add an external off-chip component to integrate in a simulation in Cadence. …
How to Create a Spice model of a discrete component in CadenceRead More »
The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground. …
Tie Cells in IC Circuits: WHY? schematic and explanationsRead More »
Creating a Verilog model cellview in Cadence for a device using a lookup table is a quick and straightforward method to characterize any physical component.
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How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-ARead More »
This auxiliary block in Cadence is a Nice to Have in your Library!
This block stops or finishes a Cadence transient simulation when an output signal reaches a desired value.
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VerilogA Code to Stop a Transient Simulation in CadenceRead More »
How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals. …
A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester. …
How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. …
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)Read More »
As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text. …
How to Setup the gedit text editor as default in Cadence for Code HighlighRead More »
How to write an ideal comparator in Cadence with vhdlams HDL language? The comparator checks if the actual input voltage pin is above the reference voltage or not.
Ideal Comparator in Cadence (VHDL-AMS) for Mixed SignalRead More »
A digital counter with N-bits is developed in VHDL in Cadence environment for mixed-signal simulations. …
A digital model and an analogue circuit of a dependent or adjustable current Source is created in Cadence.
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A variable digital controlled Current Source in CADENCERead More »