The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground. [Read more…] about Tie Cells in IC Circuits: WHY? schematic and explanations
Nmos and Pmos LDO: Differences and Advantages on each Topology
Why are the LDOs mainly built with pmos as a pass transistor and not with nmos devices? [Read more…] about Nmos and Pmos LDO: Differences and Advantages on each Topology
What are the Operation Region of Transistors in Cadence
How to know the region of operation of a single transistor in Cadence? What are the meaning of 0, 1, 2, 3 and 4 Regions in terms of cutt-off, saturation, sub-threshold, etc [Read more…] about What are the Operation Region of Transistors in Cadence
2-phase Non Overlapping Block for Oscillators
Often, we need complementary clock signals where only one clock edge is active at a time. Meaning that the rising and falling edges of the clock are separated in time. In the following diagram, we can see it clearer… [Read more…] about 2-phase Non Overlapping Block for Oscillators
Where is the 0.7V voltage drop of BJTs coming from?
Where can we obtain the ON-voltage or forward-bias voltage in bipolar transistors, which is around 0.7V? [Read more…] about Where is the 0.7V voltage drop of BJTs coming from?
How to convert a Cadence Schematic Image into White diagram
Often we deal or receive a black background the typical black-background Cadence schematic that we wish to convert to a white-background Schematic… How? [Read more…] about How to convert a Cadence Schematic Image into White diagram
