How to snap to grid a Cadence Layout
In DRC checks, the WARNING “OFFGRID vertex on layer M1 at location xx,xxx,xxx in cell XXX”. …
Cadence, Circuit Design
Circuit Design
Cadence, Circuit Design
How to Find Warning Errors in Cadence (or ignore them)
It is a bit annoying working with schematics in Cadence Virtuoso, and you “CHECK&SAVE” to see the window emerging with the same warnings you already know. …
How to Find Warning Errors in Cadence (or ignore them)Read More »
Circuit Design, Integrated Circuits
An Overview of On-chip Inductors for Integrated Circuits IC. Types, Pro & Cons
Is it possible to integrate Inductors on-chip? What kind of inductors are available in IC? Are they feasible and useful?
…
An Overview of On-chip Inductors for Integrated Circuits IC. Types, Pro & ConsRead More »
FPGA, Mixed Signal, VHDL
Clock Generator in a FPGA: Full code
How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals. …
Analog, Cadence, Circuit Design
How to performe a Monte Carlo Simulation in Cadence Virtuoso
Monte Carlo analysis is a statistical technique used to analyze the behavior of a circuit under varying conditions of PVT (Process, Voltage and Temperature) caused by manufacturing or environmental variations (temperature, voltage, mismatch, etc)
…
How to performe a Monte Carlo Simulation in Cadence VirtuosoRead More »
Cadence, Circuit Design
How to export a Plot from a Cadence Simulation to graph in Matlab
How to plot in Matlab a simulation from Cadence? How to export a Cadence graph to Matlab?
…
How to export a Plot from a Cadence Simulation to graph in MatlabRead More »
Circuit Design, Integrated Circuits
How is the Design Process of Microchips: Analog IC Design Flow to Tapeout
To fabricate a prototype of a IC chip is very expensive and it needs from several months up to 1 year to be finished. WHY???
Let’s explore all the designing steps that a CHIP requires… …
How is the Design Process of Microchips: Analog IC Design Flow to TapeoutRead More »
Cadence, Circuit Design, Mixed Signal, Verilog
Solar Cell Verilog Model for Cadence
A model of the solar cell is built in Verilog-ams. This is needed in order to perform the simulation of the MPPT in a Solar Energy Harvester. …
Cadence, Circuit Design
How to change the wire colour in Cadence
Change the color of some wires in Cadence Virtuoso can be useful in schematics with a lot of wires. …
FPGA, Mixed Signal, VHDL
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)
How to generate a high-frequency PWM signal with an FPGA (Zybo) writing a custom IP in Vivado. …
The fastest FPGA PWM Signal with Zybo and Vivado (VHDL)Read More »
Analog, Electronics
Active Filters: 2nd order Tschebychev Bandpass
A second order active bandpass filter by cascading two staggered tuned first order bandpass filters is shown, built and tested. …
Integrated Circuits
Types of IC capacitors available to integrate on chips
Pro and Cons of the different Types of IC capacitors that can be introduced in a IC chip. …
Types of IC capacitors available to integrate on chipsRead More »