How to Group Parametric Variables in Cadence
How to perform an efficient parametric simulation in Cadence Virtuoso with a parametric set of variables to reduce the simulations eliminating unuseful runs.
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Cadence, Circuit Design
Circuit Design
Analog, Cadence, Circuit Design
Example of a IC Thyristor-based ring oscillator in Cadence
IC thyristor-based oscillators offer an ultra-low-power consumption clock alternative for applications where accuracy isn’t important and a low frequency is required. …
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Electronics, Integrated Circuits
Specsmanship: Do manufacturers manipulate the specs of their components?
How trustworthy are the component specifications? Can I rely blindly on datasheets? How well is a device characterized by the manufacturer?
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Specsmanship: Do manufacturers manipulate the specs of their components? Read More »
Circuit Design, Job Interview
12 Tips to Master a Job Interview for an Entry Level Analog IC Design Position
Preparing a Job Interview for Analog IC Design positions is not easy, especially at entry-level positions where the technical questions dominate. As a fresh graduate, you need to enhance your technical and soft skills as every detail counts. …
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Cadence, Mixed Signal
How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-A
Creating a Verilog model cellview in Cadence for a device using a lookup table is a quick and straightforward method to characterize any physical component.
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How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-ARead More »
Circuit Design, Integrated Circuits
Is it Possible to Reverse Engineering a CHIP? Yes… Analog IP Piracy
Can a Microchip be copied and replicated without permission? How is this possible?
Here I will explain the Reasons and Techniques to avoid it! …
Is it Possible to Reverse Engineering a CHIP? Yes… Analog IP PiracyRead More »
Cadence, Circuit Design, Mixed Signal
VerilogA Code to Stop a Transient Simulation in Cadence
This auxiliary block in Cadence is a Nice to Have in your Library!
This block stops or finishes a Cadence transient simulation when an output signal reaches a desired value.
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Cadence, Circuit Design
How to snap to grid a Cadence Layout
In DRC checks, the WARNING “OFFGRID vertex on layer M1 at location xx,xxx,xxx in cell XXX”. …
Cadence, Circuit Design
How to Find Warning Errors in Cadence (or ignore them)
It is a bit annoying working with schematics in Cadence Virtuoso, and you “CHECK&SAVE” to see the window emerging with the same warnings you already know. …
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Circuit Design, Integrated Circuits
An Overview of On-chip Inductors for Integrated Circuits IC. Types, Pro & Cons
Is it possible to integrate Inductors on-chip? What kind of inductors are available in IC? Are they feasible and useful?
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An Overview of On-chip Inductors for Integrated Circuits IC. Types, Pro & ConsRead More »
FPGA, Mixed Signal, VHDL
Clock Generator in a FPGA: Full code
How to program an FPGA to output a square clock signal with a variable frequency and with two non-overlapping clock signals. …
Analog, Cadence, Circuit Design
How to performe a Monte Carlo Simulation in Cadence Virtuoso
Monte Carlo analysis is a statistical technique used to analyze the behavior of a circuit under varying conditions of PVT (Process, Voltage and Temperature) caused by manufacturing or environmental variations (temperature, voltage, mismatch, etc)
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