This Verilog code generates a sinus wave in FPGAs. It is done with a lookup-table and we will cover different modes with variable and fixed frequency.
A power-on reset for an FPGA is implemented in Verilog and VHDL languages. [Read more…] about Power-On Reset implementation for FPGA in Verilog and VHDL
Monte Carlo analysis is a statistical way to analyze a circuit in VLSI. [Read more…] about How to performe a Monte Carlo Simulation in Cadence Virtuoso
A bibliographic review of the state-of-the-art of carbon nanotube transistors (CNTFETs)
[Read more…] about Field-Effect Transistors based on carbon nanotubes (CNTFETs)
As a default Cadence has a non-user friendly text editor, but to code, we need to use another one like gedit. gedit is a small and lightweight text editor that allow you to highlight the text.
Analog circuits schematics are designed and simulated with ‘realistic’ models in Cadence, estimating roughly how the circuit will work in the real world. [Read more…] about Parasitic Extraction, Post-layout and Back annotating in Circuit Design