Struggling to find key parameters for transistors in Cadence? Learn how to quickly and effectively characterize NMOS devices with this comprehensive guide.
Circuit Design
Physical Comparison between NMOS vs PMOS Transistors
What are the differences between NMOS and PMOS devices in a CMOS technology?
How to Create a Spice model of a discrete component in Cadence
Frequently we need to add an external off-chip component to integrate in a simulation in Cadence.
Tie Cells in IC Circuits: WHY? schematic and explanations
The Tie Cells are small circuits used to connect (or tie) gates or input logic gates to vdd power or ground.
Nmos and Pmos LDO: Differences and Advantages on each Topology
Why are the LDOs mainly built with pmos as a pass transistor and not with nmos devices?
What are the Operation Region of Transistors in Cadence [1, 2, 3 or 4]
How to know the region of operation of a single transistor in Cadence? What are the meaning of 0, 1, 2, 3 and 4 Regions in terms of cutt-off, saturation, sub-threshold, etc