Several methods can be used to measure with Cadence Virtuoso the offset voltage of an operational amplifier (op-amp) using only simulations. …
Why Offset errors? How to Simulate the DC Offset in Op Amps with CadenceRead More »
Simulating and carrying out a proper noise analysis in Cadence is important to prevent undesired post-tapeout issues. …
How to make a Noise Analysis in Cadence step-by-stepRead More »
Struggling to find key parameters for transistors in Cadence? Learn how to quickly and effectively characterize NMOS devices with this comprehensive guide. …
How to Characterize NMOS Devices in Cadence: A Step-by-Step GuideRead More »
Frequently we need to add an external off-chip component to integrate in a simulation in Cadence. …
How to Create a Spice model of a discrete component in CadenceRead More »
How to know the region of operation of a single transistor in Cadence? What are the meaning of 0, 1, 2, 3 and 4 Regions in terms of cutt-off, saturation, sub-threshold, etc …
What are the Operation Region of Transistors in CadenceRead More »
Often we deal or receive a black background the typical black-background Cadence schematic that we wish to convert to a white-background Schematic… How? …
How to convert a Cadence Schematic Image into White diagramRead More »
There are many types of comparators, in this example a comparator with hysteresis is analyzed and simulated. …
Design a CMOS Comparator with Hysteresis in CadenceRead More »
What are the most useful keyboard shortcuts in Cadence? With these bindkeys, you will increase your productivity to work better & faster!!
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List of useful Cadence keyboard Shortcuts or Hotkeys for VirtuosoRead More »
How to perform an efficient parametric simulation in Cadence Virtuoso with a parametric set of variables to reduce the simulations eliminating unuseful runs.
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IC thyristor-based oscillators offer an ultra-low-power consumption clock alternative for applications where accuracy isn’t important and a low frequency is required. …
Example of a IC Thyristor-based ring oscillator in CadenceRead More »
Creating a Verilog model cellview in Cadence for a device using a lookup table is a quick and straightforward method to characterize any physical component.
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How to Create a new Cell in Cadence with a Loockup Table Model in Verilog-ARead More »
This auxiliary block in Cadence is a Nice to Have in your Library!
This block stops or finishes a Cadence transient simulation when an output signal reaches a desired value.
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VerilogA Code to Stop a Transient Simulation in CadenceRead More »
